There is, I think, something ethereal about i —the square root of minus one. I remember first hearing about it at school. It seemed an odd beast at that time—an intruder hovering on the edge of reality.

Usually familiarity dulls this sense of the bizarre, but in the case of i it was the reverse: over the years the sense of its surreal nature intensified. It seemed that it was impossible to write mathematics that described the real world in …

I and i

Due to its potential to greatly accelerate a wide variety of applications, reconfigurable computing has become a subject of a great deal of research. Its key feature is the ability to perform computations in hardware to increase performance, while retaining much of the flexibility of a software solution. In this survey, we explore the hardware aspects of reconfigurable computing machines, from single chip architectures to multi-chip systems, including internal structures and external coupling. We also focus on the software that targets these machines, such as compilation tools that map high-level algorithms directly to the reconfigurable substrate. Finally, we consider the issues involved in run-time reconfigurable systems, which reuse the configurable hardware during program execution.

/pdf/reconfigurable-computing-a-survey-of-systems-and-software-1bqra3qfdt.pdf

Reconfigurable computing: a survey of systems and software

International Technology Roadmap for Semiconductors 2003の要求清浄度について － シリコンウエハ表面と雰囲気環境に要求される清浄度, 分析方法の現状について －

Computational geometry

A geometric program (GP) is a type of mathematical optimization problem characterized by objective and constraint functions that have a special form. Recently developed solution methods can solve even large-scale GPs extremely efficiently and reliably; at the same time a number of practical problems, particularly in circuit design, have been found to be equivalent to (or well approximated by) GPs. Putting these two together, we get effective solutions for the practical problems. The basic approach in GP modeling is to attempt to express a practical problem, such as an engineering analysis or design problem, in GP format. In the best case, this formulation is exact; when this is not possible, we settle for an approximate formulation. This tutorial paper collects together in one place the basic background material needed to do GP modeling. We start with the basic definitions and facts, and some methods used to transform problems into GP format. We show how to recognize functions and problems compatible with GP, and how to approximate functions or data in a form compatible with GP (when this is possible). We give some simple and representative examples, and also describe some common extensions of GP, along with methods for solving (or approximately solving) them.

/pdf/a-tutorial-on-geometric-programming-47sdznbzxw.pdf

A tutorial on geometric programming

As the process technology advances to the nanometer nodes, Optical Proximity Correction (OPC) is the most popular Resolution-Enhancement Technique (RET) in industry for subwavelength lithography, and the inter-level dielectric (ILD) thickness variation caused by the planarization step of the Chemical-Mechanical Polishing (CMP) process also plays a key role for interconnect yield. Considering the OPC and CMP effects simultaneously during the routing stage can significantly alleviate the width and thickness variations (and thus the whole 3D geometry variations) of post-layout RET and CMP operations. In this paper, we first present an efficient, yet sufficiently accurate closed-form formula for printed width computation and dummy-insertion-aware routing cost derivation. The formula provides a cost modeling for post-layout OPC and CMP optimization during routing. Incorporating the OPC and CMP costs, the router can be guided to optimize the effects of layout correction and planarization. Compared with the state-of-the-art OPC-friendly router, QL-MGR (which does not consider CMP), the experimental results show that our approach can achieve respective 19% and 6% reductions in the maximum and average layout distortions. Compared with the state-of-the-art CMP-aware router, TTR (which does not consider OPC), the experimental results show that our approach can achieve respective 19% and 25% reductions in the peak-to-peak thickness and thickness variance. These results indicate that our simultaneous OPC- and CMP-aware router contributes a significant improvement for layout integrity.

/pdf/simultaneous-opc-and-cmp-aware-routing-based-on-accurate-3ccawesoz4.pdf

Simultaneous OPC- and CMP-aware routing based on accurate closed-form modeling

Disclosed herein are rouging methods and devices for a flip-chip package. The flip chip includes several outer pads and several inner pads. The routing method includes: setting an outer sequence based on the arrangement order of the outer pads; setting several inner sequences based on the connection relationships between inner pads and the outer pads; calculating the longest common subsequence of each inner sequence and the outer sequence, defining the connection relationships between the inner pads and the outer pads corresponding to the longest common subsequence as direct connections, and defining the connection relationships between the inner pads and the outer pads that do not correspond to the longest common subsequence as detour connections; establishing the routing scheme of the flip chip based on the connection relationships between the inner pads and the outer pads.

Routing Method for Flip Chip Package and Apparatus Using the Same

The present disclosure is directed to systems and methods for a minimum-implant-area (MIA) aware detailed placement. In embodiments, the present disclosure clusters a violation cell with the cells having a same threshold voltage (Vt) and determines an optimal region for a cluster to minimize the wire-length. In further embodiments, an MIA-aware cell flipping technique minimizes a design area while satisfying the MIA constraint.

Systems and methods for minimum-implant-area aware detailed placement

As technology advances apace, crosstalk becomes a design metric of comparable importance to area and delay. This article focuses mainly on the crosstalk issue, specifically on the impacts of physical design and process variation on crosstalk. While the feature size shrinks below 0.25μm, the impact of process variation on crosstalk increases rapidly. Hence, a crosstalk insensitive design is desirable in the deep submicron regime. In this article, crosstalk sensitivity is referred to as the influence of process variation on crosstalk in a circuit. We show that the lower bound of crosstalk sensitivity grows quadratically, while that of crosstalk increases linearly. Therefore, designers should also consider crosstalk sensitivity, when optimizing other design objectives such as crosstalk, area, and delay. According to our modeling, these objectives are all in posynomial forms, and thus the multi-objective optimization problem can optimally be solved by Lagrangian relaxation. Experimental results show that our method is effective and efficient. For instance, a circuit of 2856 gates and 5272 wires is optimized using 13-minute runtime and 2.8-MB memory on a Pentium III 1.0 GHz PC with 256-MB memory. In particular, by relaxing Lagrange multipliers to the critical paths, it takes only two iterations for all solutions to converge to the global optimal, which is much more efficient than related previous work. This relaxation scheme provides a key insight into the rapid convergence in Lagrangian relaxation.

https://ir.nctu.edu.tw:443/bitstream/11536/12874/1/000236871100006.pdf

Reliable crosstalk-driven interconnect optimization

We extend the quasi-particle renormalized perturbation theory developed in our previous work [Y.-W. Chang and B.-Y. Jin, J. Chem. Phys. 141, 064111 (2014)] based on nonequilibrium Green’s function techniques to study the effects of electron correlation on the charge transport process in molecular junctions. In this formalism, the single-impurity Anderson’s model is used as the zeroth-order Hamiltonian of each channel orbital, and the inter-channel interactions are treated by perturbation corrections. Within this scheme, the on-channel Coulomb repulsion and the single-particle spectral line-broadening can be incorporated in the zeroth-order approximation, and thus the Coulomb blockade and coherent tunneling through individual channels can be described properly. Beyond the zeroth-order description, electron correlation can be included through the self-energy corrections in the forms of the second-Born approximation and the GW approximation. The effects of electron correlation on molecular junctions are mani...

Yao-Wen Chang

Papers

Simultaneous OPC- and CMP-aware routing based on accurate closed-form modeling

Routing Method for Flip Chip Package and Apparatus Using the Same

Systems and methods for minimum-implant-area aware detailed placement

Reliable crosstalk-driven interconnect optimization

Theory of charge transport in molecular junctions: Role of electron correlation