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Yao-Wen Chang
Researcher at National Taiwan University
Publications - 403
Citations - 9131
Yao-Wen Chang is an academic researcher from National Taiwan University. The author has contributed to research in topics: Routing (electronic design automation) & Equal-cost multi-path routing. The author has an hindex of 45, co-authored 382 publications receiving 8378 citations. Previous affiliations of Yao-Wen Chang include MediaTek & National Chiao Tung University.
Papers
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Journal ArticleDOI
Inductance Modeling for On-Chip Interconnects
TL;DR: In this paper, the authors consider the overlapping of unequal wire lengths and dimensions to extract the loop inductance from the coplanar interconnect structure, which can be incorporated into a layout tool for inductance optimization.
Proceedings ArticleDOI
Graph matching-based algorithms for array-based FPGA segmentation design and routing
TL;DR: This paper proposes effective and efficient unified matching-based algorithms for array-based FPGA routing and segmentation design and presents a matching- based timing-driven routing algorithm which can consider a versatile set of routing segments.
Proceedings ArticleDOI
Layer minimization in escape routing for staggered-pin-array PCBs
TL;DR: This paper presents an escaped pin selection method to assign a maximal number of escaped pins in the current layer and also to increase useful routing regions for subsequent layers, and shows that this approach can significantly reduce the required layer number for escape routing.
Proceedings ArticleDOI
X-Route: An X-architecture full-chip multilevel router
Chen-Feng Chang,Yao-Wen Chang +1 more
TL;DR: A progressive X-Steiner tree algorithm based on the delaunay triangulation approach for the X-architecture is developed, which reduces the respective wirelength and average delay by about 14.05% and 30.62%, respectively.
Proceedings ArticleDOI
Timing ECO optimization using metal-configurable gate-array spare cells
TL;DR: This paper addresses a new ECO problem: Timing ECO optimization using metal-configurable gate-array spare cells, and proposes a new metric, aliveness, to model the capability of a spare gate array, and develops a timing ECO optimization framework based on al attractiveness, routability, and timing satisfaction.