Proceedings ArticleDOI
TCG: a transitive closure graph-based representation for non-slicing floorplans
Jai-Ming Lin,Yao-Wen Chang +1 more
- pp 764-769
TLDR
The geometric relation among modules is transparent not only to the TCG representation but also to its operations, facilitating the convergence to a desired solution, and makes TCG an effective and flexible representation for handling the general floorplan/placement design problems with various constraints.Abstract:
In this paper, we propose a transitive closure graph-based representation for general floorplans, called TCG, and show its superior properties. TCG combines the advantages of popular representations such as sequence pair, BSG, and B*-tree. Like sequence pair and BSG, but unlike O-tree, B*-tree, and CBL, TCG is P-admissible. Like B*-tree, but unlike sequence pair, BSG, O-tree, and CBL, TCG does not need to construct additional constraint graphs for the cost evaluation during packing, implying faster runtime. Further, TCG supports incremental update during operations and keeps the information of boundary modules as well as the shapes and the relative positions of modules in the representation. More importantly, the geometric relation among modules is transparent not only to the TCG representation but also to its operations, facilitating the convergence to a desired solution. All these properties make TCG an effective and flexible representation for handling the general floorplan/placement design problems with various constraints. Experimental results show the promise of TCG.read more
Citations
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Proceedings ArticleDOI
A thermal-driven floorplanning algorithm for 3D ICs
Jason Cong,Jie Wei,Yan Zhang +2 more
TL;DR: A thermal-driven 3D floorplanning algorithm with CBA representation that can reduce the wirelength by 29% and reduce the maximum on-chip temperature by 56% is proposed.
Journal ArticleDOI
Fixed-outline floorplanning: enabling hierarchical design
Saurabh N. Adya,Igor L. Markov +1 more
TL;DR: This paper studies the fixed-outline floorplan formulation that is more relevant to hierarchical design style and is justified for very large ASICs and SoCs and proposes new objective functions to drive simulated annealing and new types of moves that better guide local search in the new context.
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Three-Dimensional Integrated Circuit Design
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Electronic Design Automation: Synthesis, Verification, and Test
TL;DR: EDA/VLSI practitioners and researchers in need of fluency in an "adjacent" field will find this an invaluable reference to the basic EDA concepts, principles, data structures, algorithms, and architectures for the design, verification, and test of VLSI circuits.
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Global optimization of cerebral cortex layout
TL;DR: Functional areas of mammalian cerebral cortex seem positioned to minimize costs of their interconnections, down to a best-in-a-billion optimality level, which may indicate cortex optimizing mechanisms involve more global processes.
References
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