Y
Yao-Wen Chang
Researcher at National Taiwan University
Publications - 403
Citations - 9131
Yao-Wen Chang is an academic researcher from National Taiwan University. The author has contributed to research in topics: Routing (electronic design automation) & Equal-cost multi-path routing. The author has an hindex of 45, co-authored 382 publications receiving 8378 citations. Previous affiliations of Yao-Wen Chang include MediaTek & National Chiao Tung University.
Papers
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Proceedings ArticleDOI
B*-Trees: a new representation for non-slicing floorplans
TL;DR: An efficient, flexible, and effective data structure, B-trees for non-slicing floorplans, based on ordered binary trees and the admissible placement presented in [1], and a B-tree based simulated annealing scheme for floorplan design.
Journal ArticleDOI
NTUplace3: An Analytical Placer for Large-Scale Mixed-Size Designs With Preplaced Blocks and Density Constraints
TL;DR: This work proposes a high-quality analytical placement algorithm considering wirelength, preplaced blocks, and density based on the log-sum-exp wirelength model proposed by Naylor and the multilevel framework and uses the conjugate gradient method to find better macro positions.
Proceedings ArticleDOI
TCG: a transitive closure graph-based representation for non-slicing floorplans
Jai-Ming Lin,Yao-Wen Chang +1 more
TL;DR: The geometric relation among modules is transparent not only to the TCG representation but also to its operations, facilitating the convergence to a desired solution, and makes TCG an effective and flexible representation for handling the general floorplan/placement design problems with various constraints.
Book
Electronic Design Automation: Synthesis, Verification, and Test
TL;DR: EDA/VLSI practitioners and researchers in need of fluency in an "adjacent" field will find this an invaluable reference to the basic EDA concepts, principles, data structures, algorithms, and architectures for the design, verification, and test of VLSI circuits.
Journal ArticleDOI
Universal switch modules for FPGA design
TL;DR: This article presents a class of universal switch modules that can accommodate up to 25% more routing instances, compared with the XC4000-type switch module of the same size and provides a theoretical insight into the important observation by Rose and Brown [1991] that FS=3 is often sufficient to provide high routability.