Proceedings ArticleDOI
Consideration of microbump layout for reduction of local bending stress due to CTE Mismatch in 3D IC
Hisashi Kino,H. Hashiguchi,Seiya Tanikawa,Yohei Sugawara,Shunsuke Ikegaya,Takafumi Fukushima,Mitsumasa Koyanagi,Tetsu Tanaka +7 more
TLDR
This work presents design guideline of microbump layout which can suppress the local bending stress in 3D-stacked several thin IC chips to realize 3D IC with high reliability.Abstract:
Three-dimensional IC (3D IC) has attracted much attention as a promising method to enhance IC performance. Recently, great interests in mechanical reliability are increasing among 3D IC researchers for production of 3D IC. Conventional 3D ICs consist of vertically stacked several thin IC chips those are electrically connected with lots of through-Si vias (TSVs) and metal microbumps. Metal microbumps are surrounded by organic adhesive called underfill material. In general, coefficient of thermal expansion (CTE) of the underfill material is larger than that of metal microbumps. This CTE difference induces local bending stress in thinned IC chips. This local bending stress would affect transistor reliability in thinned IC chips. Therefore, we should suppress the local bending stress to realize 3D IC with high reliability. In this work, we present design guideline of microbump layout which can suppress the local bending stress in 3D-stacked several thin IC chips.read more
Citations
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Journal ArticleDOI
Effect of local stress induced by thermal expansion of underfill in three-dimensional stacked IC
Hisashi Kino,H. Hashiguchi,Seiya Tanikawa,Youhei Sugawara,Shunsuke Ikegaya,Takafumi Fukushima,Mitsumasa Koyanagi,Tetsu Tanaka +7 more
TL;DR: In this article, the effects of adhesive expansion on transistor performances were investigated by finite element method (FEM) simulation and measurement of transistor characteristics, and the authors reported their investigation results of the effect of adhesives on transistor performance.
Journal ArticleDOI
Thermo-mechanical modeling of stacked die flash memory package EMI shielding layer crack under thermal cycling test
TL;DR: In this article, a crack in the EMI layer is observed under TCT (Thermal Cycling Test) experiment, and the authors used three-dimensional thermo-mechanical FEA (Finite Element Analysis) modeling to determine the root cause of EMI shielding layer crack, that is, the two stacks of stacked NAND dies causes stress concentration and plastic strain accumulation at the eMI centerline region where the local metallic EMI structure gets fatigued and finally cracks.
Proceedings ArticleDOI
Impact of local stress in 3D stacking process on memory retention characteristics in thinned DRAM chip
TL;DR: In this article, the effect of local stresses on memory retention characteristics has been characterized in detail, and it was shown that the local stress generated by under-fill shrinkage with the dummy Cu/Sn bumps gave larger effects on the memory retention.
References
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Journal ArticleDOI
Nonlinear Thermal Stress/Strain Analyses of Copper Filled TSV (Through Silicon Via) and Their Flip-Chip Microbumps
TL;DR: In this article, the nonlinear thermal stresses and strains at the interfaces between the copper, silicon, and dielectric have been determined for a wide-range of aspect ratios (of the silicon thickness and the TSV diameter).
Journal ArticleDOI
Three-Dimensional Integration Technology Based on Wafer Bonding With Vertical Buried Interconnections
Mitsumasa Koyanagi,T. Nakamura,Yusuke Yamada,H. Kikuchi,Takafumi Fukushima,Tetsu Tanaka,Hiroyuki Kurino +6 more
TL;DR: In this article, a 3D shared-memory test chip with three-stacked layers was fabricated by bonding the wafers with vertical buried interconnections after thinning.
Proceedings ArticleDOI
Nonlinear thermal stress/strain analyses of copper filled TSV (through silicon via) and their flip-chip microbumps
TL;DR: In this article, the nonlinear thermal stresses and strains at the interfaces between the copper, silicon, and dielectric have been determined for a wide-range of aspect ratios (of the silicon thickness and the TSV diameter).
Journal ArticleDOI
Three-Dimensional Hybrid Integration Technology of CMOS, MEMS, and Photonics Circuits for Optoelectronic Heterogeneous Integrated Systems
Kang-Wook Lee,Akihiro Noriki,Koji Kiyoyama,Takafumi Fukushima,Tetsu Tanaka,Mitsumasa Koyanagi +5 more
TL;DR: The basic functions of individual chips of LSI, MEMS, and photonics devices as they were integrated into the3-D optoelectronic multichip module to verify the applied 3-D hybrid integration technology.
Proceedings ArticleDOI
Future of Strained Si/Semiconductors in Nanoscale MOSFETs
Scott E. Thompson,S. Suthram,Y. Sun,G. Sun,Srivatsan Parthasarathy,Min Chu,Toshikazu Nishida +6 more
TL;DR: In this article, the maximum electron and hole mobility enhancement for uniaxial process-induced strained silicon is modeled and experimentally measured using a flexure based 4-point wafer bending jig.