Yong-Ki Cho

TL;DR: To realize the enhanced bank access flexibility, this DRAM employs the following techniques: skewed control logic, PVT variation compensated IO sense amplifier with auto calibration by replica impedance monitor, FIFO based BLSA enable signal generator, low latency VPP generator and active jitter canceller.

TL;DR: A channel crosstalk equalizer with programmable signal ordering capability for the DRAM transmitter is presented and tri-mode clocking is addressed to reduce the system jitter for better timing margin: PLL off, LC-PLL and injection-locked oscillator.

TL;DR: In this paper, an impedance calibration circuit with a variable reference voltage generation unit was proposed to maximize the number of semiconductor devices that can be tested in test equipment at one time and permit the operation of an impedance matching unit (e.g., an on-die termination (ODT) circuit and/or an off-chip-driver) to be tested for a variety of reference resistor values.

TL;DR: In this article, a data receiver circuit includes n sampling receivers, n decision feedback equalizer (DFE) circuits, and a data recovery circuit, which is configured to select one of the n respective pre-recovery signals, and output the selected n pre recovery signal as a recovered input signal.

TL;DR: In this article, a semiconductor memory device includes a digital noise measurement circuit and an output selection circuit, which selects a first operation voltage among a plurality of operation voltages based on a voltage selection signal and outputs the first noise data.