Tae-Young Oh

TL;DR: A 1.0 V 8 Gbit LPDDR4 SDRAM with 3.2 Gbps/pin speed and integrated ECC engine for sub-1 V DRAM core is presented and the following IO features are introduced: Low voltage swing terminated logic drivers with VOH level calibration and periodic ZQ calibration, unmatched DQ/DQS scheme and DQS oscillator for D QS tree delay tracking.

TL;DR: To realize the enhanced bank access flexibility, this DRAM employs the following techniques: skewed control logic, PVT variation compensated IO sense amplifier with auto calibration by replica impedance monitor, FIFO based BLSA enable signal generator, low latency VPP generator and active jitter canceller.

TL;DR: The recent revolution in handheld computing with high-speed cellular network made mobile processors have multi-cores and powerful 3D graphic engines that support FHD (1920×1080) or even higher resolutions Consequently, the memory bandwidth requirement has also been increasing, requiring a next-generation mobile DRAM standard.

TL;DR: A channel crosstalk equalizer with programmable signal ordering capability for the DRAM transmitter is presented and tri-mode clocking is addressed to reduce the system jitter for better timing margin: PLL off, LC-PLL and injection-locked oscillator.

TL;DR: A 5.0Gbp/s/pin 8Gb LPDDR4X memory with power-isolated low-voltage-swing terminated logic (PI-LVSTL) and a split-die architecture is proposed to enhance power-efficiency and mass production yield.