Jeong-Don Lim

TL;DR: This paper proposes a 4b/cell 3D NAND Flash memory with a 12MB/s program throughput, which achieves a 5.63Gb/mm2 areal density, which is a 41.5% improvement as compared to a 3b/ cell Nander Flash memory in the same 3D-NAND technology.

TL;DR: In this article, a majority voter circuit is configured to generate a selecting signal based on first input data and inverted first input input data, and the generated selecting signal is indicative of which of the first type and the second type of bits in the input data are in the majority.

TL;DR: In this article, a data bus inversion (DBI) circuit includes at least one DBI block configured to invert an input data signal based on the logic state of input data bits.

TL;DR: To realize the enhanced bank access flexibility, this DRAM employs the following techniques: skewed control logic, PVT variation compensated IO sense amplifier with auto calibration by replica impedance monitor, FIFO based BLSA enable signal generator, low latency VPP generator and active jitter canceller.

TL;DR: A channel crosstalk equalizer with programmable signal ordering capability for the DRAM transmitter is presented and tri-mode clocking is addressed to reduce the system jitter for better timing margin: PLL off, LC-PLL and injection-locked oscillator.