C
Cheol-Goo Park
Researcher at Samsung
Publications - 5
Citations - 203
Cheol-Goo Park is an academic researcher from Samsung. The author has contributed to research in topics: Double data rate & Jitter. The author has an hindex of 5, co-authored 5 publications receiving 199 citations.
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Journal ArticleDOI
A 64-Mbit, 640-MByte/s bidirectional data strobed, double-data-rate SDRAM with a 40-mW DLL for a 256-MByte memory system
Chun-Sup Kim,Junha Lee,Jung-Hyeon Lee,Beomsup Kim,Churoo Park,Sung-Yeon Lee,Suyoun Lee,Cheol-Goo Park,J.G. Roh,Hyoungsik Nam,Du-Eung Yongin Kim,Doo-Sub Lee,Taesub Jung,Hyun-Jun Yoon,Sung-Yong Cho +14 more
TL;DR: A 64-Mbit bidirectional data strobed, double-data-rate SDRAM achieves a peak bandwidth of 2.56 GByte/s on a 64-bit-channel, 256-MByte memory system at V/sub cc/=3.3 V and T=25/spl deg/C.
Proceedings ArticleDOI
A 60nm 6Gb/s/pin GDDR5 Graphics DRAM with Multifaceted Clocking and ISI/SSN-Reduction Techniques
Seung-Jun Bae,Young-Soo Sohn,Kwang-ll Park,Kyoung-Ho Kim,Dae-Hyun Chung,Jingook Kim,Si-Hong Kim,Min-Sang Park,Jae-Hyung Lee,Sam-Young Bang,Ho-Kyung Lee,In-Soo Park,Jae-Sung Kim,Dae Hyun Kim,Hye-Ran Kim,Yong-Jae Shin,Cheol-Goo Park,Gil-Shin Moon,Ki-Woong Yeom,Kang-Young Kim,Jae-Young Lee,Hyang-ja Yang,Seong-Jin Jang,Joo Sun Choi,Young-Hyun Jun,Kinam Kim +25 more
TL;DR: This work tackles challenges in GDDR5 such as clock jitter and signal integrity with respect to forwarded clocking, data training for write and read de-skewing, clock training, channel-error detection, bank group and data coding.
Journal ArticleDOI
A 7 Gb/s/pin 1 Gbit GDDR5 SDRAM With 2.5 ns Bank to Bank Active Time and No Bank Group Restriction
Tae-Young Oh,Young-Soo Sohn,Seung-Jun Bae,Min-Sang Park,Ji-Hoon Lim,Yong-Ki Cho,Dae Hyun Kim,Dong-Min Kim,Hye-Ran Kim,Hyun-Joong Kim,Jin-Hyun Kim,Jin-Kook Kim,Young-Sik Kim,Byeong-Cheol Kim,Sang-hyup Kwak,Jae-Hyung Lee,Jae-Young Lee,Chang-Ho Shin,Yun-Seok Yang,Beom-Sig Cho,Sam-Young Bang,Hyang-ja Yang,Young-Ryeol Choi,Gil-Shin Moon,Cheol-Goo Park,Seok-Won Hwang,Jeong-Don Lim,Kwang-Il Park,Joo Sun Choi,Young-Hyun Jun +29 more
TL;DR: To realize the enhanced bank access flexibility, this DRAM employs the following techniques: skewed control logic, PVT variation compensated IO sense amplifier with auto calibration by replica impedance monitor, FIFO based BLSA enable signal generator, low latency VPP generator and active jitter canceller.
Proceedings ArticleDOI
A 40nm 2Gb 7Gb/s/pin GDDR5 SDRAM with a programmable DQ ordering crosstalk equalizer and adjustable clock-tracking BW
Seung-Jun Bae,Young-Soo Sohn,Tae-Young Oh,Si-Hong Kim,Yun-Seok Yang,Dae Hyun Kim,Sang-hyup Kwak,Ho-Seok Seol,Chang-Ho Shin,Min-Sang Park,Gong-Heom Han,Byeong-Cheol Kim,Yong-Ki Cho,Hye-Ran Kim,Su-Yeon Doo,Young-Sik Kim,Dong-seok Kang,Young-Ryeol Choi,Sam-Young Bang,sunyoung park,Yong-Jae Shin,Gil-Shin Moon,Cheol-Goo Park,Woo-Seop Kim,Hyang-ja Yang,Jeong-Don Lim,Kwang-Il Park,Joo Sun Choi,Young-Hyun Jun +28 more
TL;DR: A channel crosstalk equalizer with programmable signal ordering capability for the DRAM transmitter is presented and tri-mode clocking is addressed to reduce the system jitter for better timing margin: PLL off, LC-PLL and injection-locked oscillator.
Proceedings ArticleDOI
A 640 MB/s bi-directional data strobed, double-data-rate SDRAM with a 40 mW DLL circuit for a 256 MB memory system
TL;DR: This 256 MB memory system achieves 256 Gb/s peak bandwidth with a 160 MHz clock and 64b channel using a /spl plusmn/0.4 V-swing, push-pull type I/O interface (SSTL).