Manufacturing and measurement of freeform optics

A method and system for performing layout verification on an integrated circuit (IC) design using reusable subdesigns. Many custom designed integrated circuits are designed and fabricated using a number of computer implemented automatic design processes. Within these processes, a high level design language (e.g., HDL or VHDL) description of the integrated circuit can be translated by a computer system into a netlist of technology specific gates and interconnections there between. The cells of the netlist are then placed spatially in an integrated circuit layout and the connections between the cells are routed using computerized place and route processes. Circuit designers next run layout verification tests on the layout to verify that the geometry and connectivity data of the design meets specific design rules and matches logically with the schematic representation. The present invention provides a method of layout verification where unchanged subdesigns of a hierarchical IC design can be reused upon subsequent verification processes of the same IC design. They are reused for both design rule checking (DRC) and layout versus schematic (LVS) comparison. By reusing some of the subcell designs, subsequent verification processes of the present invention can be performed very efficiently. To account for faults attributed to subcell interfaces, the present invention advantageously determines subcell overlap areas within the layout and selectively flattens and verifies these areas in addition to any subcell designs that were not previously validated. Further, the invention determines updated connectivity information for new subcell designs.

Method and system for layout verification of an integrated circuit design with reusable subdesigns

Techniques are provided for extending the use of phase shift techniques to implementation of masks used for complex layouts in the layers of integrated circuits, beyond selected critical dimension features. The method includes identifying features for which phase shifting can be applied, automatically mapping the phase shifting regions for implementation of such features, resolving phase conflicts which might occur according to a given design rule, and application of assist features and proximity correction features. The method includes applying an adjustment to a phase shift mask pattern including a first and a second phase shift window, and a control chrome with a control width, and/or to a trim mask pattern having a trim shape with a trim width based upon one or both of a rule based correction and a model based correction to improve a match between a resulting exposure pattern and a target feature.

Phase shift masking for complex patterns with proximity adjustments

Phase information is incorporated into a cell-based design methodology Standard cells have four edges: top, bottom, left, and right The top and bottom edges have fixed phase shifters placed, eg 0 A given cell C will have a phase set created with two versions: 0-180 (left-right) as well as 180-0 Alternatively, the same phase set: 0—0 and 180—180 could be created for a cell The phase sets are selected based on the ability to phase shift the features within the cell C By creating a phase set for most of the cells of a cell library, standard cell placement and routing techniques can be used and phase can then be quickly assigned using a simple ripple technique This ensures a phase compliant design upfront for the standard cell areas In some instances, phase sets are created for every cell in a library

Standard cell design incorporating phase information

A method of generating patterns of a pair of photomasks from a data set defining a circuit layout to be provided on a substrate includes identifying critical segments of the circuit layout to be provided on the substrate. Block mask patterns are generated and then legalized based on the identified critical segments. Thereafter, phase mask patterns are generated, legalized and colored. The legalized block mask patterns and the legalized phase mask patterns that have been colored define features of a block mask and an alternating phase shift mask, respectively, for use in a dual exposure method for patterning features in a resist layer of a substrate.

Generating mask patterns for alternating phase-shift mask lithography

A process for creating and verifying a design of phase-shifted masks utilizing at least one phase shift region employing a computer-aided design system. A chip design is provided. A phase-shift mask design capable of producing the chip design is created. Features in a design of the phase-shifted mask that require phase shifting are located. Uncolored phase regions are created on opposite sides of the features. Proper phase termination of the phase regions is ensured based upon space constraints of a phase-shifted mask technique utilized. Phases are determined for the phase regions. Whether coloring errors and un-phase-shiftable design features exist is determined. Mask process specific overlaps and expansions are applied to the mask design to prepare designed data levels for mask manufacture. A residual phase edge image removal design is derived.

Phase shifted mask design system, phase shifted mask and VLSI circuit devices manufactured therewith

According to the preferred embodiment, a method is provided for automatically coloring VLSI design elements for the purpose of assigning binary properties to the elements. The preferred method is particularly applicable for use generating phase shift mask designs from VLSI CAD datasets. The preferred method uses net coloring to automatically generate a data set of colored elements. The preferred method is not dependent on the order in which the elements are operated upon. The preferred method has the additional advantage of being able to automatically detect conflicts that prevent the VLSI design from being optimally colored. The preferred method is equally applicable to hierarchical VLSI databases with nested components and traditional flat databases. When applied the hierarchical databases, the preferred method provides element coloring with minimal data flattening required.

Automatic generation of phase shift masks using net coloring

We demonstrate experimentally for the first time the feasibility of applying SMO technology using pixelated illumination. Wafer images of SRAM contact holes were obtained to confirm the feasibility of using SMO for 22nm node lithography. There are still challenges in other areas of SMO integration such as mask build, mask inspection and repair, process modeling, full chip design issues and pixelated illumination, which is the emphasis in this paper. In this first attempt we successfully designed a manufacturable pixelated source and had it fabricated and installed in an exposure tool. The printing result is satisfactory, although there are still some deviations of the wafer image from simulation prediction. Further experiment and modeling of the impact of errors in source design and manufacturing will proceed in more detail. We believe that by tightening all kind of specification and optimizing all procedures will make pixelated illumination a viable technology for 22nm or beyond.

Publisher's Note: The author listing for this paper has been updated to include Carsten Russ. The PDF has been updated to reflect this change.

Experimental result and simulation analysis for the use of pixelated illumination from source mask optimization for 22nm logic lithography process

A computer-based system and method is provided for creating a representation of interconnections between VLSI circuit design components. A VLSI circuit design component identifying a leaf design entity is stored in memory. Placements in the design where the design component appears are stored in memory. A set of links is formed to connect placements to one another. The links further specify placement of the design component in the circuit design. The interconnections themselves are then computed. The interconnections denote where placements of the VLSI circuit design component instances are interconnected, and may specify any meaningful coupling, such as electrical conductivity, magnetic, or optical. The interconnections are represented by a nested net graph which includes a list of nets, and instance counts associated with the nets. The nested net graph may also include a second list, which specifies instances of lower nested nets contained in the nested net graph. The nested net graph may further include a shape-to-net table attached at the root of the nested net graph. The shape-to-net table defines a mapping from the VLSI circuit design component to a corresponding net. Also provided is a system and method for building interconnections using a bridge component, or bridge net. The bridge net denotes the interconnection between two nets derived from a pair of VLSI circuit design component instances.

System and method for building interconnections in a hierarchical circuit design

An efficient method for modifying a chip or package design allows for the creation of small shapes without excessive expansion of design data. A computer program takes a physical design, represented in a computer data file, and generates a modified version of the design in which fill shapes have been added. Subsequently, when the modified design is processed, the resulting semiconductor chip or package will contain physical images of the added fill shapes, with the effect of making local pattern density more uniform and hence reducing process-induced variations in feature size and shape.

Young O. Kim

Papers

Phase shifted mask design system, phase shifted mask and VLSI circuit devices manufactured therewith

Automatic generation of phase shift masks using net coloring

Experimental result and simulation analysis for the use of pixelated illumination from source mask optimization for 22nm logic lithography process

System and method for building interconnections in a hierarchical circuit design

Efficient generation of fill shapes for chips and packages