Zeynep Toprak-Deniz

TL;DR: This paper presents an iVRM system developed for the POWER8™ microprocessor, which functions as a very fast, accurate low-dropout regulator (LDO), with 90.5% peak power efficiency (only 3.1% worse than an ideal LDO).

TL;DR: A dual-loop architecture employs eight distributed microregulators (UREGs) to achieve load response times below 500 ps in 45-nm SOI CMOS to reduce the output ripple generated by switching the pMOS passgate on and off.

TL;DR: This paper presents a 32 Gb/s non-return-to-zero optical link using 850-nm vertical-cavity surface-emitting laser-based multi-mode optics with 14-nm bulk FinFET CMOS circuits for integration on to the first-level package to increase package I/O bandwidth density and lower overall system power and cost.

TL;DR: POWER8™ is a 12-core processor fabricated in IBM's 22 nm SOI technology with core and cache improvements driven by big data applications, providing 2.5× socket performance over POWER7+™, and power efficiency is improved with several techniques.

TL;DR: In this article, a dual-loop voltage regulator circuit is implemented with a first inner loop having a bang-bang voltage regulator to achieve nearly instantaneous response time, and a second outer loop, which is slower in operating speed than the first inner-loop, to controllably adjust a trip point of the Bang-Bang voltage regulator.