Timothy O. Dickson

TL;DR: The feasibility of integrating antennas and required circuits to form wireless interconnects in foundry digital CMOS technologies has been demonstrated and the key challenges including the effects of metal structures associated with integrated circuits, heat removal, packaging, and interaction between transmitted and received signals, and nearby circuits appear to be manageable.

TL;DR: In this paper, planar and three-dimensional inductors and transformers were designed and characterized on-wafer up to 100 GHz, and the first time that spiral structures are suitable for applications such as 60-GHz wireless local area network and 77-GHz automotive RADAR.

TL;DR: Evidence is provided that, as a result of constant-field scaling, the peak fT, peak fMAX, and optimum noise figure NFMIN current densities of Si and SOI n-channel MOSFETs are largely unchanged over technology nodes and foundries, and constant current-density biasing schemes are proposed to be applied to M OSFET analog/mixed-signal/RF and high-speed digital circuit design.

TL;DR: In this article, it was shown that the current densities of Si and SOI n-channel MOSFETs are largely unchanged over technology nodes and foundries, and that the characteristic current density also remains invariant for the most common circuit topologies such as MOS-SiGe HBT cascodes, MOS CML gates, and nMOS transimpedance amplifiers (TIAs) with active pMOS FET loads.

TL;DR: A compact and power-efficient serial I/O targeting dense silicon carrier interconnects is reported, which features low-impedance transmitter termination, high-IMpedance receiver termination, and a receiver with modified DFE with IIR filter feedback (DFE-IIR).