There is, I think, something ethereal about i —the square root of minus one. I remember first hearing about it at school. It seemed an odd beast at that time—an intruder hovering on the edge of reality.

Usually familiarity dulls this sense of the bizarre, but in the case of i it was the reverse: over the years the sense of its surreal nature intensified. It seemed that it was impossible to write mathematics that described the real world in …

I and i

“Unpaired Image-to-Image Translation using Cycle-Consistent Adversarial Networks”の学習報告

Various log-likelihood-ratio-based belief-propagation (LLR-BP) decoding algorithms and their reduced-complexity derivatives for low-density parity-check (LDPC) codes are presented. Numerically accurate representations of the check-node update computation used in LLR-BP decoding are described. Furthermore, approximate representations of the decoding computations are shown to achieve a reduction in complexity by simplifying the check-node update, or symbol-node update, or both. In particular, two main approaches for simplified check-node updates are presented that are based on the so-called min-sum approximation coupled with either a normalization term or an additive offset term. Density evolution is used to analyze the performance of these decoding algorithms, to determine the optimum values of the key parameters, and to evaluate finite quantization effects. Simulation results show that these reduced-complexity decoding algorithms for LDPC codes achieve a performance very close to that of the BP algorithm. The unified treatment of decoding techniques for LDPC codes presented here provides flexibility in selecting the appropriate scheme from performance, latency, computational-complexity, and memory-requirement perspectives.

Reduced-complexity decoding of LDPC codes

Initial efforts on wireless power transfer (WPT) have concentrated toward long-distance transmission and high power applications. Nonetheless, the lower achievable transmission efficiency and potential health concerns arising due to high power applications, have caused limitations in their further developments. Due to tremendous energy consumption growth with ever-increasing connected devices, alternative wireless information and power transfer techniques have been important not only for theoretical research but also for the operational costs saving and for the sustainable growth of wireless communications. In this regard, radio frequency energy harvesting (RF-EH) for a wireless communications system presents a new paradigm that allows wireless nodes to recharge their batteries from the RF signals instead of fixed power grids and the traditional energy sources. In this approach, the RF energy is harvested from ambient electromagnetic sources or from the sources that directionally transmit RF energy for EH purposes. Notable research activities and major advances have occurred over the last decade in this direction. Thus, this paper provides a comprehensive survey of the state-of-art techniques, based on advances and open issues presented by simultaneous wireless information and power transfer (SWIPT) and WPT assisted technologies. More specifically, in contrast to the existing works, this paper identifies and provides a detailed description of various potential emerging technologies for the fifth generation communications with SWIPT/WPT. Moreover, we provide some interesting research challenges and recommendations with the objective of stimulating future research in this emerging domain.

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Simultaneous Wireless Information and Power Transfer (SWIPT): Recent Advances and Future Challenges

algorithmics and modular computations, Theory of Codes and Cryptography (3).From an analytical 1. RE Blahut. Theory and practice of error control codes. eecs.uottawa.ca/∼yongacog/courses/coding/ (3) R.E. Blahut,Theory and Practice of Error Control Codes, Addison Wesley, 1983. QA 268. Cached. Download as a PDF 457, Theory and Practice of Error Control CodesBlahut 1984 (Show Context). Citation Context..ontinued fractions.

Theory and practice of error control codes

Low-density parity-check (LDPC) codes constructed over the Galois field GF(q), which are also called nonbinary LDPC codes, are an extension of binary LDPC codes with significantly better performance. Although various kinds of low-complexity quasi-optimal iterative decoding algorithms have been proposed, the VLSI implementation of nonbinary LDPC decoders has rarely been discussed due to their hardware unfriendly properties. In this brief, an efficient selective computation algorithm, which totally avoids the sorting process, is proposed for Min-Max decoding. In addition, an efficient VLSI architecture for a nonbinary Min-Max decoder is presented. The synthesis results are given to demonstrate the efficiency of the proposed techniques.

An Efficient VLSI Architecture for Nonbinary LDPC Decoders

This paper studies low-complexity high-speed decoder architectures for quasi-cyclic low density parity check (QC-LDPC) codes. Algorithmic transformation and architectural level optimization are incorporated to reduce the critical path. Enhanced partially parallel decoding architectures are proposed to linearly increase the throughput of conventional partially parallel decoders through introducing a small percentage of extra hardware. Based on the proposed architectures, a (8176, 7154) Euclidian geometry-based QC-LDPC code decoder is implemented on Xilinx field programmable gate array (FPGA) Virtex-II 6000, where an efficient nonuniform quantization scheme is employed to reduce the size of memories storing soft messages. FPGA implementation results show that the proposed decoder can achieve a maximum (source data) decoding throughput of 172 Mb/s at 15 iterations

Low-Complexity High-Speed Decoder Design for Quasi-Cyclic LDPC Codes

This paper presents a high-throughput decoder design for the Quasi-Cyclic (QC) Low-Density Parity-Check (LDPC) codes. Two new techniques are proposed, including parallel layered decoding architecture (PLDA) and critical path splitting. PLDA enables parallel processing for all layers by establishing dedicated message passing paths among them. The decoder avoids crossbar-based large interconnect network. Critical path splitting technique is based on articulate adjustment of the starting point of each layer to maximize the time intervals between adjacent layers, such that the critical path delay can be split into pipeline stages. Furthermore, min-sum and loosely coupled algorithms are employed for area efficiency. As a case study, a rate-1/2 2304-bit irregular LDPC decoder is implemented using ASIC design in 90 nm CMOS process. The decoder can achieve the maximum decoding throughput of 2.2 Gbps at 10 iterations. The operating frequency is 950 MHz after synthesis and the chip area is 2.9 mm2.

High-throughput layered decoder implementation for quasi-cyclic LDPC codes

This paper presents a high-throughput decoder architecture for generic quasi-cyclic low-density parity-check (QC-LDPC) codes. Various optimizations are employed to increase the clock speed. A row permutation scheme is proposed to significantly simplify the implementation of the shuffle network in LDPC decoder. An approximate layered decoding approach is explored to reduce the critical path of the layered LDPC decoder. The computation core is further optimized to reduce the computation delay. It is estimated that 4.7 Gb/s decoding throughput can be achieved at 15 iterations using the current technology.

High-Throughput Layered LDPC Decoding Architecture

In this paper, we analyze the finite precision effects on the decoding performance of Gallager's low density parity check (LDPC) codes and develop optimal finite word lengths of variables as far as the tradeoffs between the performance and hardware complexity are concerned. We have found that 4 bits and 6 bits are adequate for representing the received data and extrinsic information, respectively. Simulation results indicate that the quantization scheme we have developed for the LDPC decoder is effective in approximating the infinite precision implementation.

Zhongfeng Wang

Papers

An Efficient VLSI Architecture for Nonbinary LDPC Decoders

Low-Complexity High-Speed Decoder Design for Quasi-Cyclic LDPC Codes

High-throughput layered decoder implementation for quasi-cyclic LDPC codes

High-Throughput Layered LDPC Decoding Architecture

On finite precision implementation of low density parity check codes decoder