Initial efforts on wireless power transfer (WPT) have concentrated toward long-distance transmission and high power applications. Nonetheless, the lower achievable transmission efficiency and potential health concerns arising due to high power applications, have caused limitations in their further developments. Due to tremendous energy consumption growth with ever-increasing connected devices, alternative wireless information and power transfer techniques have been important not only for theoretical research but also for the operational costs saving and for the sustainable growth of wireless communications. In this regard, radio frequency energy harvesting (RF-EH) for a wireless communications system presents a new paradigm that allows wireless nodes to recharge their batteries from the RF signals instead of fixed power grids and the traditional energy sources. In this approach, the RF energy is harvested from ambient electromagnetic sources or from the sources that directionally transmit RF energy for EH purposes. Notable research activities and major advances have occurred over the last decade in this direction. Thus, this paper provides a comprehensive survey of the state-of-art techniques, based on advances and open issues presented by simultaneous wireless information and power transfer (SWIPT) and WPT assisted technologies. More specifically, in contrast to the existing works, this paper identifies and provides a detailed description of various potential emerging technologies for the fifth generation communications with SWIPT/WPT. Moreover, we provide some interesting research challenges and recommendations with the objective of stimulating future research in this emerging domain.

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Simultaneous Wireless Information and Power Transfer (SWIPT): Recent Advances and Future Challenges

We show that successive cancellation list decoding can be formulated exclusively using log-likelihood ratios. In addition to numerical stability, the log-likelihood ratio based formulation has useful properties that simplify the sorting step involved in successive cancellation list decoding. We propose a hardware architecture of the successive cancellation list decoder in the log-likelihood ratio domain which, compared with a log-likelihood domain implementation, requires less irregular and smaller memories. This simplification, together with the gains in the metric sorter, lead to $ 56\%$ to $137\%$ higher throughput per unit area than other recently proposed architectures. We then evaluate the empirical performance of the CRC-aided successive cancellation list decoder at different list sizes using different CRCs and conclude that it is important to adapt the CRC length to the list size in order to achieve the best error-rate performance of concatenated polar codes. Finally, we synthesize conventional successive cancellation decoders at large block-lengths with the same block-error probability as our proposed CRC-aided successive cancellation list decoders to demonstrate that, while our decoders have slightly lower throughput and larger area, they have a significantly smaller decoding latency.

LLR-Based Successive Cancellation List Decoding of Polar Codes

Cloud computing draws significant attention in the information technology (IT) community as it provides ubiquitous on-demand access to a shared pool of configurable computing resources with minimum management effort. It gains also more impact on the communication technology (CT) community and is currently discussed as an enabler for flexible, cost-efficient and more powerful mobile network implementations. Although centralized baseband pools are already investigated for the radio access network (RAN) to allow for efficient resource usage and advanced multicell algorithms, these technologies still require dedicated hardware and do not offer the same characteristics as cloud-computing platforms, i.e., on-demand provisioning, virtualization, resource pooling, elasticity, service metering, and multitenancy. However, these properties of cloud computing are key enablers for future mobile communication systems characterized by an ultradense deployment of radio access points (RAPs) leading to severe multicell interference in combination with a significant increase of the number of access nodes and huge fluctuations of the rate requirements over time. In this article, we will explore the benefits that cloud computing offers for fifth-generation (5G) mobile networks and investigate the implications on the signal processing algorithms.

Benefits and Impact of Cloud Computing on 5G Signal Processing: Flexible centralization through cloud-RAN

A method and system for decoding low density parity check (“LDPC”) codes. An LDPC decoder includes an R select unit, a Q message first-in first-out (“FIFO”) memory, and a cyclic shifter. The R select unit provides an R message by selecting from a plurality of possible R message values. The Q message memory stores a Q message until an R message is generated by a CNU, the Q message and the R message are combined to provide a P message. The cyclic shifter shifts the P message.

Low density parity check decoder for regular LDPC codes

This paper presents a high-throughput decoder architecture for generic quasi-cyclic low-density parity-check (QC-LDPC) codes. Various optimizations are employed to increase the clock speed. A row permutation scheme is proposed to significantly simplify the implementation of the shuffle network in LDPC decoder. An approximate layered decoding approach is explored to reduce the critical path of the layered LDPC decoder. The computation core is further optimized to reduce the computation delay. It is estimated that 4.7 Gb/s decoding throughput can be achieved at 15 iterations using the current technology.

High-Throughput Layered LDPC Decoding Architecture

Low-density parity-check (LDPC) codes constructed over the Galois field GF(q), which are also called nonbinary LDPC codes, are an extension of binary LDPC codes with significantly better performance. Although various kinds of low-complexity quasi-optimal iterative decoding algorithms have been proposed, the VLSI implementation of nonbinary LDPC decoders has rarely been discussed due to their hardware unfriendly properties. In this brief, an efficient selective computation algorithm, which totally avoids the sorting process, is proposed for Min-Max decoding. In addition, an efficient VLSI architecture for a nonbinary Min-Max decoder is presented. The synthesis results are given to demonstrate the efficiency of the proposed techniques.

An Efficient VLSI Architecture for Nonbinary LDPC Decoders

The classification of white blood cells is critical for the diagnosis of anemia, leukemia and many other hematologic diseases. Current approaches are mainly based on traditional machine learning methods, which take quite a noticeable time and the recognition error rate is relatively high especially for the rare kinds of leukocytes. In this paper, we develop an automatic cell recognition system by applying deep learning methods. The results demonstrate that the proposed system performs well in the leukocytes recognition task with less hardware limitations and higher accuracy compared to the traditional ones.

Automatic classification of leukocytes using deep neural network

This paper addresses decoder design for nonbinary quasicyclic low-density parity-check (QC-LDPC) codes. First, a novel decoding algorithm is proposed to eliminate the multiplications over Galois field for check node processing. Then, a partially parallel architecture for check node processing units and an optimized architecture for variable node processing units are developed based on the new decoding algorithm. Thereafter, an efficient decoder structure dedicated to a promising class of high-performance nonbinary QC-LDPC codes is presented for the first time. Moreover, an ASIC implementation for a (620, 310) nonbinary QC-LDPC code decoder over GF(32) is designed to demonstrate the efficiency of the presented techniques.

Efficient Decoder Design for Nonbinary Quasicyclic LDPC Codes

Low-density parity-check (LDPC) codes are one of the most promising error-correcting codes approaching Shannon capacity and have been adopted in many applications. However, the efficient implementation of high-throughput LDPC decoders adaptable for various channel conditions still remains challenging. In this paper, a low-complexity reconfigurable VLSI architecture for high-speed LDPC decoders is presented. Shift-LDPC codes are incorporated within the design and have shown not only comparable decoding performance to computer-generated random codes but also high hardware efficiency in high-speed applications. The single-minimum Min-Sum decoding scheme and the nonuniform quantization scheme are explored to reduce the complexity of computing core and the memory requirement. The well-known Benes network is employed to construct the configurable permutation network to support multiple shift-LDPC codes with various code parameters. The ASIC implementation results of an (8192, 7168) (4, 32)-regular shift-LDPC decoder demonstrate a maximum decoding throughput of 3.6 Gbits/s at 16 iterations, which outperforms the state-of-the-art design for high-speed flexible LDPC decoders by many times with even less hardware.

Flexible LDPC Decoder Design for Multigigabit-per-Second Applications

Low-Density Parity-check (LDPC) code, being one of the most promising near-Shannon limit error correction codes (ECCs) in practice, has attracted tremendous attention in both academia and industry since its rediscovery in middle 1990's. Owning excellent coding gain, LDPC code also has very low error floor, and inherent parallizable decoding schemes. Compared to other ECCs such as Turbo codes, BCH codes and RS codes, LDPC code has many more varieties in code construction, which result in various optimum decoding architectures associated with different structures of the parity-check matrix. In this work, we first provide an overview of typical LDPC code structures and commonly-used LDPC decoding algorithms. We then discuss efficient VLSI architectures for random-like codes and structured LDPC codes. We further present layered decoding schemes and corresponding VLSI architectures. Finally we briefly address non-binary LDPC decoding and multi-rate LDPC decoder design.

Jin Sha

Papers

An Efficient VLSI Architecture for Nonbinary LDPC Decoders

Automatic classification of leukocytes using deep neural network

Efficient Decoder Design for Nonbinary Quasicyclic LDPC Codes

Flexible LDPC Decoder Design for Multigigabit-per-Second Applications

VLSI Design for Low-Density Parity-Check Code Decoding