Viable cryptosystem designs must address power analysis attacks, and masking is a commonly proposed technique for defending against these side-channel attacks It is possible to overcome simple masking by using higher-order techniques, but apparently only at some cost in terms of generality, number of required samples from the device being attacked, and computational complexity We make progress towards ascertaining the significance of these costs by exploring a couple of attacks that attempt to efficiently employ second-order techniques to overcome masking In particular, we consider two variants of second-order differential power analysis: Zero-Offset 2DPA and FFT 2DPA

Towards efficient second-order power analysis

Low Cost Cryptography.- Quark: A Lightweight Hash.- PRINTcipher: A Block Cipher for IC-Printing.- Sponge-Based Pseudo-Random Number Generators.- Efficient Implementations I.- A High Speed Coprocessor for Elliptic Curve Scalar Multiplications over .- Co-Z Addition Formulae and Binary Ladders on Elliptic Curves.- Efficient Techniques for High-Speed Elliptic Curve Cryptography.- Side-Channel Attacks and Countermeasures I.- Analysis and Improvement of the Random Delay Countermeasure of CHES 2009.- New Results on Instruction Cache Attacks.- Correlation-Enhanced Power Analysis Collision Attack.- Side-Channel Analysis of Six SHA-3 Candidates.- Tamper Resistance and Hardware Trojans.- Flash Memory 'Bumping' Attacks.- Self-referencing: A Scalable Side-Channel Approach for Hardware Trojan Detection.- When Failure Analysis Meets Side-Channel Attacks.- Efficient Implementations II.- Fast Exhaustive Search for Polynomial Systems in .- 256 Bit Standardized Crypto for 650 GE - GOST Revisited.- Mixed Bases for Efficient Inversion in and Conversion Matrices of SubBytes of AES.- SHA-3.- Developing a Hardware Evaluation Method for SHA-3 Candidates.- Fair and Comprehensive Methodology for Comparing Hardware Performance of Fourteen Round Two SHA-3 Candidates Using FPGAs.- Performance Analysis of the SHA-3 Candidates on Exotic Multi-core Architectures.- XBX: eXternal Benchmarking eXtension for the SUPERCOP Crypto Benchmarking Framework.- Fault Attacks and Countermeasures.- Public Key Perturbation of Randomized RSA Implementations.- Fault Sensitivity Analysis.- PUFs and RNGs.- An Alternative to Error Correction for SRAM-Like PUFs.- New High Entropy Element for FPGA Based True Random Number Generators.- The Glitch PUF: A New Delay-PUF Architecture Exploiting Glitch Shapes.- New Designs.- Garbled Circuits for Leakage-Resilience: Hardware Implementation and Evaluation of One-Time Programs.- ARMADILLO: A Multi-purpose Cryptographic Primitive Dedicated to Hardware.- Side-Channel Attacks and Countermeasures II.- Provably Secure Higher-Order Masking of AES.- Algebraic Side-Channel Analysis in the Presence of Errors.- Coordinate Blinding over Large Prime Fields.

Cryptographic hardware and embedded systems : CHES 2010 : 12th international workshop, Santa Barbara, USA, August 17-20, 2010 : proceedings

Side-Channel Analysis 1.- Attack and Improvement of a Secure S-Box Calculation Based on the Fourier Transform.- Collision-Based Power Analysis of Modular Exponentiation Using Chosen-Message Pairs.- Multiple-Differential Side-Channel Collision Attacks on AES.- Implementations 1.- Time-Area Optimized Public-Key Engines: -Cryptosystems as Replacement for Elliptic Curves?.- Ultra High Performance ECC over NIST Primes on Commercial FPGAs.- Exploiting the Power of GPUs for Asymmetric Cryptography.- Fault Analysis 1.- High-Performance Concurrent Error Detection Scheme for AES Hardware.- A Lightweight Concurrent Fault Detection Scheme for the AES S-Boxes Using Normal Basis.- RSA with CRT: A New Cost-Effective Solution to Thwart Fault Attacks.- Random Number Generation.- A Design for a Physical RNG with Robust Entropy Estimators.- Fast Digital TRNG Based on Metastable Ring Oscillator.- Efficient Helper Data Key Extractor on FPGAs.- Side-Channel Analysis 2.- The Carry Leakage on the Randomized Exponent Countermeasure.- Recovering Secret Keys from Weak Side Channel Traces of Differing Lengths.- Attacking State-of-the-Art Software Countermeasures-A Case Study for AES.- Cryptography and Cryptanalysis.- Binary Edwards Curves.- A Real-World Attack Breaking A5/1 within Hours.- Hash Functions and RFID Tags: Mind the Gap.- Implementations 2.- A New Bit-Serial Architecture for Field Multiplication Using Polynomial Bases.- A Very Compact Hardware Implementation of the MISTY1 Block Cipher.- Light-Weight Instruction Set Extensions for Bit-Sliced Cryptography.- Fault Analysis 2.- Power and Fault Analysis Resistance in Hardware through Dynamic Reconfiguration.- RFID and Its Vulnerability to Faults.- Perturbating RSA Public Keys: An Improved Attack.- Side-Channel Analysis 3.- Divided Backend Duplication Methodology for Balanced Dual Rail Routing.- Using Subspace-Based Template Attacks to Compare and Combine Power and Electromagnetic Information Leakages.- Mutual Information Analysis.- Invited Talks.- RSA-Past, Present, Future.- A Vision for Platform Security.

Cryptographic hardware and embedded systems : CHES 2008 : 10th International Workshop, Washington, D.C., USA, August 10-13, 2008 : proceedings

Hash Function Cryptanalysis.- Security of MD5 Challenge and Response: Extension of APOP Password Recovery Attack.- Cryptanalysis of a Hash Function Based on Quasi-cyclic Codes.- Linear-XOR and Additive Checksums Don't Protect Damgard-Merkle Hashes from Generic Attacks.- Cryptographic Building Blocks.- Efficient Fully-Simulatable Oblivious Transfer.- Separation Results on the "One-More" Computational Problems.- Fairness in Secure Computation.- An Efficient Protocol for Fair Secure Two-Party Computation.- Efficient Optimistic Fair Exchange Secure in the Multi-user Setting and Chosen-Key Model without Random Oracles.- Legally-Enforceable Fairness in Secure Two-Party Computation.- Message Authentication Codes.- Security of NMAC and HMAC Based on Non-malleability.- Aggregate Message Authentication Codes.- Improved AES Implementations.- Boosting AES Performance on a Tiny Processor Core.- A Fast and Cache-Timing Resistant Implementation of the AES.- Public Key Encryption with Special Properties.- Identity-Based Threshold Key-Insulated Encryption without Random Oracles.- CCA2 Secure IBE: Standard Model Efficiency through Authenticated Symmetric Encryption.- Public-Key Encryption with Non-interactive Opening.- Side Channel Cryptanalysis.- A Vulnerability in RSA Implementations Due to Instruction Cache Analysis and Its Demonstration on OpenSSL.- Fault Analysis Study of IDEA.- Susceptibility of UHF RFID Tags to Electromagnetic Analysis.- Cryptography for Limited Devices.- Online/Offline Signature Schemes for Devices with Limited Computing Capabilities.- RFID Security: Tradeoffs between Security and Efficiency.- Invited Talk.- Program Obfuscation and One-Time Programs.- Key Exchange.- Efficient Two-Party Password-Based Key Exchange Protocols in the UC Framework.- Beyond Secret Handshakes: Affiliation-Hiding Authenticated Key Exchange.- Cryptanalysis.- Improving the Efficiency of Impossible Differential Cryptanalysis of Reduced Camellia and MISTY1.- Small Secret Key Attack on a Variant of RSA (Due to Takagi).- Cryptographic Protocols.- Super-Efficient Verification of Dynamic Outsourced Databases.- A Latency-Free Election Scheme.

Topics in Cryptology - CT-RSA 2008 : the Cryptographers' Track at the RSA Conference 2008 San Fancisco, CA, USA, April 8-11, 2008 : proceedings

Key exchange protocols establish a secret key to confidentially communicate digital information over public channels. Lattice-based key exchange protocols are a promising alternative for next-generation applications due to their quantum-cryptanalysis resistance and implementation efficiency. While these constructions rely on the theory of quantum-resistant lattice problems, their practical implementations have shown vulnerability against side-channel attacks in the context of public-key encryption or digital signatures. Applying such attacks on key exchange protocols is, however, much more challenging because the secret key changes after each execution of the protocol, limiting the side-channel adversary to a single measurement. In this paper, we demonstrate the first successful power side-channel attack on lattice-based key exchange protocols. The attack targets the hardware implementation of matrix and polynomial multiplication used in these protocols. The crux of our idea is to apply a horizontal attack that makes hypothesis on several intermediate values within a single execution all relating to the same secret and to combine their correlations for accurately estimating the secret key. We illustrate that the design of key exchange protocols combined with the nature of lattice arithmetic enables our attack. Since a straightforward attack suffers from false positives, we demonstrate a novel procedure to recover the key by following the sequence of intermediate updates during multiplication. We analyzed two key exchange protocols, NewHope (USENIX'16) and Frodo (CCS'16), and show that their implementations can be vulnerable to our attack. We test the effectiveness of the proposed attack using concrete parameters of these protocols on a physical platform with real measurements. On a SAKURA-G FPGA Board, we show that the proposed attack can estimate the entire secret key from a single power measurement with over 99% success rate.

Horizontal side-channel vulnerabilities of post-quantum key exchange protocols

NTRU cryptosystem has been suggested for protecting wireless body area networks, which is secure in the sense of traditional cryptanalysis. In this paper, we fulfill the first power analysis attack on the ultra-low-power environment of wireless body area networks. Specifically, two practical differential power analyses on NTRU algorithm are proposed, which can attack the existing countermeasures of NTRU. Accordingly, we suggest three countermeasures against our attacks. Meanwhile, practical experiments show that although the attacks in this paper are efficient, our countermeasures can resist them effectively.

Power Analysis Attacks and Countermeasures on NTRU-Based Wireless Body Area Networks

In 2011, Li presented clockwise collision analysis on nonprotected Advanced Encryption Standard (AES) hardware implementation. In this brief, we first propose a new clockwise collision attack, called fault rate analysis (FRA), on masked AES. Then, we analyze the critical and noncritical paths of the S-box and find that, for its three input bytes, namely, the input value, the input mask, and the output mask, the path relating to the output mask is much shorter than those relating to the other two inputs. Therefore, some sophisticated glitch cycles can be chosen such that the values in the critical path of the whole S-box are destroyed but this short path is not affected. As a result, the output mask does not offer protection to the S-box, which leads to a more efficient attack. Compared with three attacks on masking countermeasures at the Workshop on Cryptographic Hardware and Embedded Systems 2010 and 2011, our method only costs about 8% of their time and 4% of their storage space.

Fault Rate Analysis: Breaking Masked AES Hardware Implementations Efficiently

Edge computing handles delay-sensitive data and provides real-time feedback, while it brings data security issues to edge devices (such as IoT devices and edge servers). Side-channel attacks main threaten to these devices. Collision attack represents a powerful category of side-channel analysis in extracting security information from embedded cryptographic algorithms. Since its proposition in 2003, plenty of collision detection algorithms are presented, most of which enumerate all the values of target plaintext byte to find a collision. In this paper, we establish a relation between “Euclidean distance between traces” and “Hamming distance between values,” and take advantage of the distance information leaked from the power traces of encrypting an adaptively chosen plaintext to reduce the candidate plaintext space. Consequently, the collision is detected at a high pace. Moreover, this improvement is fault-tolerant, and its self-correction feature promotes the efficiency of attacks based on our method significantly. We take AES implemented with masks, which is usually employed in edge computing devices, for instance, to introduce our method and conduct experiments to verify its efficiency. According to the experimental results, for whole key recovery attacks, our method requires only 26.5% plaintexts, 32.2% traces, and much less than 10% computations of the collision-correlation attack launched by Clavier et al.

/pdf/adaptive-chosen-plaintext-collision-attack-on-masked-aes-in-18otz0qsko.pdf

Adaptive Chosen-Plaintext Collision Attack on Masked AES in Edge Computing

Collision attack is often employed against some cryptographic algorithms such as AES and DES. As a usual countermeasure, masking can resist such attacks to some extent. In CHES 2011, Clavier et al. proposed a collision-correlation attack based on Pearson correlation coefficient against masking. In this paper, a collision distinguisher based on least absolute deviation against masking is proposed. Subsequently, we suggest three other distinguishers based on least square method, least exponent method, and central moment product, respectively. Our experiments and simulations show that in practice, our distinguishers based on least absolute deviation and least square method perform much better than collision-correlation attack and other proposed distinguishers in this paper. We also give four application examples, which show that even if the masks are not reused, new distinguishers are competent to collision attacks.

Efficient collision attacks on smart card implementations of masked AES

Due to low Signal to Noise Ratio (SNR) in general experimental environments, previous attack methods such as correlation power analysis (CPA) do not always screen out the correct key value. Sometimes the success rate of the attack is so slight that we have to find other ways to make certain of the prosperity. In this paper, rather than adopting the traditional means of singling out a single key value, we suggest a way of setting up a threshold for the attack. Accordingly, we propose a feasible method to filter the inherently enlarging candidate key space, which is called correlation-template-induction attack. The method contains three steps: First, we apply a variation of CPA and get a set of candidate key values. Then, we filter the candidate key space with template attack, which is easy to implement and requires encryptions of just a few input data to screen out the correct key. Next, to achieve optimal of our attack, we mix the concept of induction together with our attack. The experimental results given in this article on an AES smart card implementation guarantee the effectiveness of our method.

Zongyue Wang

Papers

Power Analysis Attacks and Countermeasures on NTRU-Based Wireless Body Area Networks

Fault Rate Analysis: Breaking Masked AES Hardware Implementations Efficiently

Adaptive Chosen-Plaintext Collision Attack on Masked AES in Edge Computing

Efficient collision attacks on smart card implementations of masked AES

Overcoming significant noise: correlation-template-induction attack