International Conference on Design and Technology of Integrated Systems in Nanoscale Era 

About: International Conference on Design and Technology of Integrated Systems in Nanoscale Era is an academic conference. The conference publishes majorly in the area(s): CMOS & System on a chip. Over the lifetime, 566 publications have been published by the conference receiving 2866 citations.

A survey on simulation-based fault injection tools for complex systems

Abstract: Dependability is a key decision factor in today's global business environment. A powerful method that permits to evaluate the dependability of a system is the fault injection. The principle of this approach is to insert faults into the system and to monitor its responses in order to observe its behavior in the presence of faults. Several fault injection techniques and tools have been developed and experimentally tested. They could be mainly grouped into three categories: hardware fault injection, simulation-based fault injection, and emulation-based fault injection. This paper presents a survey on the simulation-based fault injection techniques, with a focus on complex micro-processor based systems.

Wearable Energy Harvesting: From body to battery

Abstract: Energy Harvesting (EH) technologies provide promising solutions to overcome the short lifetime of wearable devices In the last decade, EH has matured as a technology and found use in many application scenarios, such as smart grid and wireless sensor networks Recently, advances have been made in miniaturizing EH devices to supply wearable devices by exploiting ambient energy in the form of motion, thermal gradients, light and electromagnetic radiation However, harvesting energy from the body for powering wearable devices is more challenging due to strict constraints in terms of size, weight and cost In this paper, we present a taxonomy of technologies, architectures and design trade-offs for efficient EH systems suitable for wearable devices Additionally, we provide implementation details, including the conversion stages for kinetic and thermal EH, optimized for the human body We quantify the energy that it is possible to harvest in real application scenarios, which is in the range of 200–700 mJ per day, depending the source, and result in up to 15 J per day if coupled The design guidelines and experimental evaluations we present, with in-field measurement, will be of benefit to designers of future EH wearable systems

Memristor based memories: Technology, design and test

Abstract: Today's memory technologies, such as DRAM, SRAM, and NAND Flash, are facing major challenges with regard to their continued scaling. For instance, ITRS projects that DRAM cannot scale easily below 40nm as the cost and energy/power are hard -if not impossible- to scale. Fortunately, the international memory technology community has been researching other alternative for more than fifteen years. Apparently, non-volatile resistive memories are promising to replace the today's memories for many reasons such as better scalability, low cost, higher capacity, lower energy, CMOS compatibility, better configurability, etc. This paper discusses and highlights three major aspects of resistive memories, especially memristor based memories: (a) technology and design constraints, (b) architectures, and (c) testing and design-for-test. It shows the opportunities and the challenges.

Hardware acceleration of sequence alignment algorithms-an overview

Abstract: Sequence alignment is one of the most important activities in bioinformatics. With the ever increasing volume of data in bioinformatics databases, the time for comparing a query sequence with the available databases is always increasing. Many algorithms have been proposed to perform and accelerate sequence alignment activities. This paper introduces a taxonomy of the various sequence alignment algorithms found in the literature, with particular emphasis on the Smith-Waterman (S-W) algorithm. The paper also provides a classification of the available hardware acceleration methods used to speed up the S-W algorithm.

Efficient hardware architecture of recursive Karatsuba-Ofman multiplier

Abstract: The finite Field multiplication is the basic operation in all cryptographic applications. It can be performed by using Serial, Booth, Montgomery and Karatsuba-Ofman's divide-and-conquer technique. The Karatsuba-Ofman multiplier replaces a multiplication by three ones of half-length operands which are performed in parallel. The implementation of Karatsuba-Ofman multiplier has been made both in sequential and parallel architectures. In order to improve the performance's architectures over GF (2m), we propose a new Sequential/Parallel architectures of Recursive Karatsuba-Ofman multiplier. In this paper, two Sequential/Parallel architectures are presented, developed and implemented on the Spartan 3 FPGA platform. Area and low Delay computation of the proposed architectures are improved. Mathematical Performances models (Area (n), Delay (n)) for large number (n) are elaborated for our proposed architectures. They can be established in order to expect the appropriate multiplier for the cryptographic applications.