Showing papers by "Amkor Technology published in 1999"

Thin, stackable semiconductor packages

Abstract: A thin, stackable semiconductor package having improved electrical and heat dissipating performance comprises a semiconductor chip having an integrated circuit and a plurality of input/output pads on a surface thereof. A lead frame having a plurality of inner leads with upper and a lower surfaces has one of those surfaces bonded to a surface of the chip with a bonding agent. The leads each has a projection formed on at least one of the upper and lower surfaces at a distal end portion of the lead. Each of the leads is electrically connected to an associated input/output pad of the chip through a wire bonding process using electrically conductive wires, or by a ball bonding process using electrically conductive balls. Alternatively, the leads may be directly bonded to the input/output pads of the chip by a TAB bonding process. An encapsulated portion envelops the semiconductor chip and the leads while exposing the projections of the leads to the atmosphere outside the encapsulated portion. A solder ball is welded to the bottom surface of the projection of each lead and is used as a signal input/output terminal of the package. A chip heat sink may be bonded to the chip to further increase the capacity of the package to dissipate heat away from the chip during operation.

Plastic integrated circuit package and method and leadframe for making the package

Abstract: Packages for an integrated circuit die and methods and leadframes for making such packages are disclosed. The package includes a die, a die pad, peripheral metal contacts, bond wires, and an encapsulant. The die pad and contacts are located at a lower surface of the package. The die pad and the contacts have side surfaces which include reentrant portions and asperities to engage the encapsulant. A method of making a package includes providing a metal leadframe having a die pad in a rectangular frame. Tabs extend from the frame toward the die pad. The die pad and tabs have side surfaces with reentrant portions and asperities. A die is attached to the die pad. The die is electrically connected to the tabs. An encapsulant is applied to the upper and side surfaces of the leadframe. Finally, the leadframe is cut in situ so that the die pad and tabs are severed from the frame, the sides of the package are formed, and the package is severed from the leadframe.

Molded window array for image sensor packages

Abstract: Image sensor packages are fabricated simultaneously to minimize the cost associated with each individual image sensor package. To fabricate the image sensor packages, windows are molded in molding compound to form a molded window array. A substrate includes a plurality of individual substrates integrally connected together in an array format. Image sensors are attached and electrically connected to corresponding individual substrates. An adhesive layer attaches the molded window array to the substrate. The substrate and attached molded window array are singulated into a plurality of individual image sensor packages.

Electronic device package and leadframe and method for making the package

Abstract: The present invention includes a package for housing an integrated circuit device. The present invention also includes leadframes and methods for making such packages. The package includes an integrated circuit device on a metal die pad. A metal ring is between the die pad and leads and surrounds the die pad. The ring is connected to the die pad by a nonconductive tape. Encapsulant material covers the entire structure. The ring is connected to a lead identified for connection to an external power voltage supply. The ring in turn is connected to a power voltage input pad on the integrated circuit device. The die pad floats, or is connected to a lead that is connected to an external ground voltage. The package is made from a leadframe that has a die pad, a metal ring between the die pad and radiating leads, and a nonconductive tape that connects the ring to the die pad. In one embodiment, the leadframe and package also include a bypass or decoupling capacitor attached between the die pad and the ring.

Semiconductor package and method for fabricating the same

Abstract: A semiconductor package and a method of making the package are disclosed. The package includes a semiconductor chip having first surface with a conductive pad thereon. A first end of a bond wire is connected to each of the pads. Encapsulant covers the fist surface of the chip, the pads, and the bond wires, and forms side surfaces of the package. A second end of the bond wires is exposed at a side surface of the package. Making the package includes providing a wafer including a plurality of semiconductor chip units. Each chip unit has a plurality of conductive pads at a first surface of the wafer. A bond wire is electrically connected between each pad of each semiconductor chip unit and a pad of at least one adjacent semiconductor chip unit of the wafer. An encapsulant is applied onto the first surface of the wafer so as to completely cover the bond wires and pads of the semiconductor units. The encapsulated wafer is separated between adjacent semiconductor chip units so as to sever the bond wires and form individual packages each having side surfaces formed of the encapsulant. A severed end of each bond wire is exposed at a side surface of the respective package.

Chip-size semiconductor packages

Abstract: A wafer-level method for mass production of surface-mounting, chip-size (“CS”) ball grid array (“BGA”), land grid array (“LGA”), and lead-less chip carrier (“LCC”) semiconductor packages includes the wire-bond or flip-chip attachment of ceramic substrates to the active surface of corresponding chips while they are still integral to a semiconductor wafer, thereby reducing manufacturing costs of the packages relative to that of individually packaged chips The substrates have a thermal coefficient of expansion (TCE) closely matching that of the underlying chip This eliminates the need for a silicone “interposer” between the substrate and the chip otherwise necessary to prevent stress-related problems caused by the difference in the respective thermal expansion and contraction of the chip and substrate with changes in temperature, further reducing the cost of the packages, improving heat transfer from the chips, and resulting in a package that is relatively free of thermal-induced stresses

Plastic package for an optical integrated circuit device and method of making

Abstract: A package for an integrated circuit device having an optical cell is disclosed. A method of making the package also is disclosed. The package includes a base of molded encapsulant material. A metal leadframe is embedded in the plastic base at the upper surface of the base. Encapsulant material covers the lower and side surfaces of the die pad and the leads of the leadframe, but does not cover the upper surfaces of the die pad and leads. The side surfaces of the die pad and leads have locking features for engaging the encapsulant material. An optical integrated circuit device is attached to the exposed surface of the die pad. An adhesive bead is applied around the optical device on the exposed upper surface of the leads. An optically clear cover is placed on and, in some embodiments, pressed into the still-viscous adhesive bead. When hardened, the bead supports the cover above the optical device. The side surfaces of the optically clear cover, or the surface of the cover facing the optical device, are provided with locking features that engage the adhesive bead and strengthen the connection between the cover and the adhesive bead.

Integrated circuit package having adhesive bead supporting planar lid above planar substrate

Abstract: A package for an integrated circuit is described, as are methods of making the package. The package includes a substrate having a generally planar first surface on which a metal die pad is formed. An integrated circuit die is attached to the metal die pad. An adhesive head surrounds the integrated circuit die and covers the exposed periphery of the metal die pad. A generally planar lid is in a press-fitted interconnection with the bead. An adhesive material covers conductive structures on the die, such as bonding pads, to prevent corrosion. Optionally, the package has vertical peripheral sides. The methods of making the package include methods for making packages individually, or making a plurality of packages simultaneously. Where a plurality of packages are made simultaneously, integrated circuit die are placed on each of a plurality of physically-joined package substrates on a generally planar sheet of substrate material. An adhesive bead is applied around each die. In cross-section, the bead has a central peak and a shorter peak on each side of the central peak. A sheet of lid material is placed onto the beads. After the bead is hardened, individual packages are formed by cutting the substrate sheet, lid sheet, and beads.

Chip-scale semiconductor package of the fan-out type and method of manufacturing such packages

Abstract: Chip-scale semiconductor packages of the fan-out type and methods of manufacturing such packages are disclosed. In one package embodiment within the invention, the package substrate is stiff enough to effectively carry an increased number of solder balls on an exterior area outside the edge of a semiconductor chip, in addition to the area above the chip. In another package embodiment, a molded support is mounted to the lower surface of the exterior area. The methods of the present invention include making a plurality of packages on a substrate. Prior to sawing a wafer to obtain chips for the assembly method, the wafer is inspected so as to discriminate between good chips and the defective chips. Only good chips are mounted to a wafer-shaped or strip-shaped substrate.

Thin image sensor package

Abstract: A thin image sensor package includes an image sensor having an active area which is responsive to radiation. The image sensor is mounted to a substrate which is transparent to the radiation. The image sensor is mounted such that the active area of the image sensor faces the substrate. Of importance, the substrate serves a dual function. In particular, the substrate is the window which covers the active area of the image sensor. Further, the substrate is the platform upon which the image sensor package is fabricated. As a result, the image sensor package is thin, lightweight and inexpensive to manufacture.

Plastic integrated circuit device package and method of making the same

Abstract: A package for an integrated circuit device, having a die, a die pad, leads, bond wire, and an encapsulant. The lower surfaces of the die pad and the leads are provided with stepped profiles. Structures extending from lateral sides of the leads are formed to prevent the leads from being pulled horizontally from the package. Encapsulant material fills beneath the recessed, substantially horizontal surfaces of the die pad and the leads, and thereby prevents the die pad and the leads from being pulled vertically from the package body. Other portions of the die pad and the leads are exposed within the package for connecting the package externally.

Shear testing and failure mode analysis for evaluation of BGA ball attachment

Abstract: With increasing focus on BGA technology as a high performance package, there is an urgent need to develop industry-wide standards for package quality and reliability. A significant factor in BGA package quality is the robustness of solder ball attachment to the package. Currently, ball shear testing is used to assess solder joint integrity. The solder ball failure mechanism can not be determined from shear force data alone, but is critical to understanding solder joint quality. A failure mode analysis, along with a fundamental understanding of the shear test process, is needed to assess solder joint quality. A common pad finish on BGA packages and PWB substrates is Ni/Au, using either electrolytic or electroless deposition. There are reports of brittle fracture in BGA and PWB interconnects with both types of Ni/Au surface finishes. During post-assembly test and manufacturing, the solder to pad interconnection has been shown to separate under certain conditions. In this study, ball shear testing is performed in conjunction with thermal preconditioning to evaluate brittle fractures on a thermally enhanced BGA with electroless Ni/Au bond pads and on a plastic BGA with electrolytic Ni/Au bond pads. Cross sectioning and fractography reveal interfacial failure in both package types. However, metallography and SEM with EDX confirm two distinct interfacial failure mechanisms. The failure analysis is interpreted in terms of the implications for package quality and performance. Although this evaluation is performed on BGA packages, the failure analysis results are applicable to brittle fractures on PWBs using a Ni/Au surface finish.

Optical sensor array mounting and alignment

Abstract: A method and apparatus for mounting an optical sensor to, and in optical alignment with, a lens or other imaging-forming element of an optical device includes attaching a fixture to the lens, the fixture having mounting features located thereon at predetermined positions measured relative to the focal plane of the lens, the optical axis of the lens, and the horizontal and vertical axes of a scene imaged by the lens. The absolute locations of the plane, the center, and the horizontal and vertical axes of the sensor array are found within and independently of the sensor package using automated optical pattern recognition apparatus. Using numerically controlled apparatus, complementary mounting features are then milled into the sensor package at positions measured relative to the absolute locations of the sensor features found by the pattern recognition equipment that correspond to the predetermined positions of the mounting features on the fixture measured relative to the optical features of the lens.

Methods of making thin integrated circuit device packages with improved thermal performance and substrates for making the packages

Abstract: Methods of making integrated circuit device packages and substrates for making the packages are disclosed. An embodiment of a method of making a substrate includes providing an unpatterned sheet of polyimide material having a first surface and an opposite second surface. A planar metal layer is attached to the second surface of the polyimide sheet. The metal layer is patterned to form an array of package sites, with each site including a planar die pad and planar leads. Apertures are formed through the polyimide sheet, either before or after attaching the metal layer. Each aperture is juxtaposed with a lead allowing access thereto. A method of making a package using the substrate includes mounting an integrated circuit device above the die pad (e.g., on the substrate or on the die pad through an aperture in the substrate). Bond wires are connected between the integrated circuit device and the leads through the apertures. An insulative encapsulant is applied so as to cover the integrated circuit device and fill the apertures. A method of making multiple packages includes a final step of cutting an encapsulated array of package sites with a saw to separate individual packages.

Thin leadframe-type semiconductor package having heat sink with recess and exposed surface

Abstract: A thin, small-outline semiconductor package, and a thermally enhanced leadframe for use in it, comprise a plurality of electrically conductive leads held together in a spaced, planar relationship about a central opening defined by the leads, and a thick, plate-like heat sink made of an electrically and thermally conductive metal attached to the leads such that it is centered within the opening and parallel to the plane of the leads. The heat sink has a lower surface exposed through the outer surface of a molded resin envelope encapsulating the package for the efficient dissipation of heat therefrom, and an upper surface having a recess formed into it. The recess has a planar floor with a semiconductor die attached to it, and defines a grounding ring around the periphery of the upper surface of the heat sink immediately adjacent to the edges of the die for the down-bonding of grounding wires from the die and the leads. The package provides enhanced heat dissipating capabilities, an improved resistance to long-term penetration by moisture, and a down-bonding region that substantially shortens the length of grounding wires down-bonded thereto and substantially reduces the residual shear stress acting on the down-bonds.

Snap lid image sensor package

Abstract: An image sensor package includes a molding having a locking feature The package further includes a snap lid having a tab, where the tab is attached to the locking feature of the molding To form the image sensor package, a window is placed in a pocket of the molding The snap lid is secured in place Once secured, the snap lid presses against a peripheral region of an exterior surface of the window The window is sandwiched between the molding and the snap lid and held in place

Method of molding plastic semiconductor packages

Abstract: In the manufacture of semiconductor packages having molded plastic bodies, the plating of all of the surfaces of the molding tool that comes into contact with the molten resin during molding with a nodular thin dense chromium (“NTDC”) coating prevents the surfaces from adhering to the package body and ensures good package release, without formation of cracks or craters in the package body. This, in turn, permits the amount of both release agents and adhesion promoters used in the molding compound to be substantially reduced, or eliminated altogether, thereby resulting in a package body having improved strength and adhesion with the components of the package, and hence, an improved resistance of the package body to the propagation of cracks and its subsequent penetration by moisture.

Printed circuit board with oval solder ball lands for BGA semiconductor packages

Abstract: A PCB having oval solder ball lands, and a BGA semiconductor package produced using such a PCB, are disclosed. The PCB has a plurality of conductive traces forming circuit patterns on at least one of an upper and a lower surface of a resin substrate. A plurality of solder ball lands are formed on the lower surface of the substrate and are electrically connected to respective upper surface conductive traces. At least a portion of the solder ball lands have an oval shape and a major axis. The oval solder ball lands are oriented such that their major axes are either radially directed relative to a center of the substrate, perpendicularly directed relative to a side edge of the substrate, or both radially and perpendicularly directed relative the center and a side edge of the substrate, respectively. Solder balls welded to the oval lands have an improved strength capable of effectively resisting a shearing stress caused by a thermal expansion of the PCB during operation of a semiconductor chip, and the BGA package thus has a prolonged fatigue life. The oval solder ball lands also enlarge the width of a neck point between adjacent solder ball lands, thereby enabling a larger number of conductive traces to pass through the neck point.

Microcircuit die-sawing protector and method

Abstract: A method and apparatus for protecting hypersensitive microcircuits on the face of a semiconductor wafer from contamination and mechanical damage during die sawing and subsequent die handling operations include the provision of a plastic sheet having an array of protective domes formed into it, the array corresponding to the array of microcircuits on the wafer, and the temporary adhesion of the sheet to the face of the wafer such that each die in the wafer is covered by a respective one of the domes, with an associated one of the microcircuits protectively sealed therein. Die sawing is performed with the component side of the wafer facing up, the cut passing between the domes and through the thicknesses of both the domed sheet and the wafer such that each die is separated from the wafer, with a corresponding one other domes still attached to it. The domes may be removed later when the dies are located in a more benign environment by simply peeling them off the die. The invention enables the use of conventional die-handling equipment and results in improved device yield.

Method of assembling a snap lid image sensor package

Abstract: An image sensor package includes a molding having a locking feature. The package further includes a snap lid having a tab, where the tab is attached to the locking feature of the molding. To form the image sensor package, a window is placed in a pocket of the molding. The snap lid is secured in place. Once secured, the snap lid presses against a peripheral region of an exterior surface of the window. The window is sandwiched between the molding and the snap lid and held in place.

Lead frame used for the fabrication of semiconductor packages and semiconductor package fabricated using the same

Abstract: A lead frame for a semiconductor package including a rectangular lead frame body having a central opening, a plurality of leads arranged at and along each of two or four facing sides of the lead frame body, the leads extending in flush with the lead frame body, and a semiconductor chip mounting plate positioned on a plane not flush with a plane, where the leads are positioned, the semiconductor chip mounting plate being supported by down-set tie bars and provided with at least one groove having a rectangular ring shape while serving to prevent a penetration of moisture and to provide an increased coupling strength for the semiconductor chip mounting plate, the semiconductor chip mounting plate also serving as a heat sink. A ground bridge bar having a rectangular ring shape is arranged between the semiconductor chip mounting plate and the leads and supported by another tie bars. By virtue of the bridge bar, the length of bonding wires is reduced, thereby eliminating the possibility of the bonding wires to be short-circuited. A lead frame having a double down-set structure is also provided. By virtue of the double down-set structure, it is possible to increase the size of the semiconductor chip mounting plate, thereby achieving an improvement in the heat discharge effect.

Method of fabricating image sensor packages in an array

Abstract: Image sensor packages are fabricated simultaneously to minimize the cost associated with each individual image sensor package. To fabricate the image sensor packages, windows are molded in molding compound to form a molded window array. A substrate includes a plurality of individual substrates integrally connected together in an array format. Image sensors are attached and electrically connected to corresponding individual substrates. An adhesive layer attaches the molded window array to the substrate. The substrate and attached molded window array are singulated into a plurality of individual image sensor packages.

Method of forming an integrated circuit device package using a plastic tape as a base

Abstract: Methods for forming packages for housing an integrated circuit device are disclosed. In one embodiment, step 1 provides a plastic sheet having an adhesive first surface. Step 2 provides a patterned metal sheet on the first surface of the plastic sheet. The patterned metal sheet includes an array of package sites. Each package site is formed to include a die pad and a plurality of leads around the die pad. Step 3 places an integrated circuit device on each of the die pads. Step 4 connects a conductor between the integrated circuit device and the leads of the respective package site. Step 5 applies an encapsulating material onto the array. Step 6 hardens the encapsulating material. Step 7 removes the first plastic sheet. Step 8 applies solder balls to the exposed surfaces of the leads. Finally, step 9 separates individual packages from the encapsulated array. The side surfaces of the die pad and leads of the package include a reentrant portion for engaging the encapsulant material and locking the die pad and leads to the package.

Thin image sensor package fabrication method

Abstract: A thin image sensor package includes an image sensor having an active area which is responsive to radiation The image sensor is mounted to a substrate which is transparent to the radiation The image sensor is mounted such that the active area of the image sensor faces the substrate Of importance, the substrate serves a dual function In particular, the substrate is the window which covers the active area of the image sensor Further, the substrate is the platform upon which the image sensor package is fabricated As a result, the image sensor package is thin, lightweight and inexpensive to manufacture

Molded image sensor package

Abstract: An image sensor package includes a molding having an interior locking feature and an exterior locking feature. The molding is a low cost molded part. The image sensor package further includes a window having an interior surface and an exterior surface. The exterior locking feature of the molding contacts a periphery of the exterior surface of the window and the interior locking feature of the molding contacts a periphery of the interior surface of the window. In this manner, the window is supported by the molding both top and bottom. Also, the distance which moisture must travel along the interface between the molding and window to reach the image sensor is maximized thus essentially eliminating moisture ingress into the image sensor package.

Method of molding ball grid array semiconductor packages

Abstract: A method of molding BGA semiconductor packages comprises grounding a PCB in the package to a grounded mold during the process of molding the package, thus preventing an accumulation of electrostatic charge on the components of the BGA package, thereby preventing any damage to the semiconductor chips, bonding wires or conductive traces in the package resulting from a sudden discharge of such an accumulated charge. The means for grounding the PCB may include grounding projections on one of the molds, and/or may comprise grounding pads, grounding bosses, or grounding tooling holes in the PCB. The grounding projections on the mold are positioned on opposite sides of a runner in the mold. The grounding pads or bosses are electrically connected to a ground via hole and a ground trace, and, in one embodiment are positioned on the bottom surface of the PCB outside of a package separation line. The grounding tooling hole is internally plated with a conductive metal layer to receive and make an electrical contact with a conductive tooling pin extending from one of the molds.

Are we over designing for solder joint reliability? Field vs. accelerated conditions, realistic vs. specified requirements

Abstract: The recent trend towards miniaturization is requiring engineers to look for packages which are near chip size and have finer pitch I/Os with small solder joints. Although the reliability of solder joints may not meet the field life requirements in some cases the engineer may have to select a package that is not optimum for electrical and thermal performance, may not meet size and density requirements or does not meet price targets. Faced with such a situation, an engineer is forced to ask whether the reliability requirements are realistic and if the system is being over designed to meet those requirements? This paper seeks to answer these questions. An industry survey of reliability requirements for various applications is presented, showing inconsistencies within industry groups. Various thermal cycle field conditions are discussed and a validated life prediction approach is used to determine the acceleration factors from field to accelerated test conditions. A comparison is made between realistic and specified reliability requirements for various applications to determine if the systems are being over designed. Acceleration factors for different test conditions are also presented to help sort out the published data on solder joint reliability.

Conductive strap attachment process that allows electrical connector between an integrated circuit die and leadframe

Abstract: A method of making an integrated circuit package is disclosed. A conductive first adhesive is applied onto a leadframe pad of a leadframe. A conductive second adhesive is applied on an input portion of the leadframe, such as a leadframe member that is integral with inner portions of input leadfingers. An integrated circuit die, such as a power MOSFET, is placed on the first adhesive on the leadframe pad. A conductive third adhesive is applied onto a surface of the integrated circuit die opposite the leadframe pad. A conductive strap is placed on the third adhesive on the integrated circuit die and on the second adhesive on the leadframe. The first, second and third adhesives are then simultaneously cured so that the integrated circuit die is permanently attached to the leadframe pad, and the conductive strap is permanently attached to the die and the leadframe member.

Wafer-scale production of chip-scale semiconductor packages using wafer mapping techniques

Abstract: A method is disclosed for manufacturing chip-scale semiconductor packages at a wafer-scale level using wafer mapping techniques. In the method, a semiconductor wafer and/or a circuit substrate, each respectively comprising a plurality of individual chips and circuit pattern units, is/are pre-tested and discriminated in terms of the quality and/or grade of each individual chip unit and/or circuit pattern unit contained therein. The test results are marked on the lower surface of each chip unit and/or on each pattern unit. The substrate is laminated to the wafer to form a laminated assembly prior to performing the packaging process, which typically includes a wire bonding step, an encapsulation step and a solder ball welding step. A plurality of connected package units are thereby formed in the laminated substrate-wafer assembly. The package units are then singulated from each other and the laminated assembly by a cutting process. Using the pre-testing results, the method eliminates wasteful packaging of defective chips. The quality and/or grade of packaged units are marked on the chips in accordance with the pre-testing data, thereby enabling defective packages to be distinguished from good packages without need for post-singulation testing. The method permits using only good circuit pattern units, thereby preventing expensive chip units from being packaged with defective pattern units. In addition, the method permits both a package pick-and-place step and a package marking step to be combined into a single operation using a single device.

Circuit pattern tape for wafer-scale production of chip size semiconductor packages

Abstract: A circuit pattern tape for the wafer-scale production of chip size semiconductor packages is adapted to be laminated onto a semiconductor wafer and includes a flexible insulating layer, a plurality of identical circuit pattern units arrayed thereon, and a solder mask covering the circuit patterns. Each circuit pattern unit includes a central opening, a plurality of bond fingers arranged on opposite sides of the opening and electrically connected through the opening to associated die pads on an underlying semiconductor chip in the wafer, a plurality of solder ball lands, each having a solder ball attached thereto, and a plurality of conductive traces electrically connecting respective ones of the bond fingers and the solder ball lands to each other. The bond fingers and central opening are arranged so that they do not intersect singulation lines defining the coincident edges of the corresponding individual circuit pattern units and chips after they are cut from the wafer-tape assembly, thereby eliminating chipping of the wafer. The circuit pattern units may include a dummy pattern that is made of the same conductive metal as the solder ball lands, the conductive traces, and the bond fingers, and which is arranged on the circuit pattern to achieve a uniform distribution of the conductive metal thereon and thereby minimize voids between the tape and the wafer and bowing in the dissimilar materials of the tape due to a change in its temperature.