Showing papers by "Amkor Technology published in 2013"

Wafer level package and fabrication method

Abstract: A method of forming an electronic component package includes coupling a first surface of an electronic component to a first surface of a first dielectric strip, the electronic component comprising bond pads on the first surface; forming first via apertures through the first dielectric strip to expose the bond pads; and filling the first via apertures with an electrically conductive material to form first vias electrically coupled to the bond pads. The bond pads are directly connected to the corresponding first vias without the use of a solder and without the need to form a solder wetting layer on the bond pads.

Exposed die overmolded flip chip package and fabrication method

Abstract: An exposed die overmolded flip chip package includes a substrate. A die is flip chip mounted to an upper surface of the substrate. The package further includes a mold cap filling a space between an active surface of the die and the upper surface of the substrate. The mold cap includes a principal surface, sidewalls extending from the upper surface of the substrate to the principal surface, an annular surface coplanar with the inactive surface of the die and extending outward from a peripheral edge of the inactive surface of the die, and protruding surfaces extending between the principal surface and the annular surface. The mold cap does not cover the inactive surface of the die such that heat transfer from the die to the ambient environment is maximized and the package thickness is minimized.

Shielded package having shield lid

Abstract: A shielded package includes a shield assembly having a shield fence, a shield lid, and a shield lid adhesive electrically coupling the shield lid to the shield fence. The shield fence includes a porous sidewall through which molding compound passes during molding of the shielded package. Further, the shield fence includes a central aperture through which an electronic component is die attached and wire bonded.

Wafer level fan-out package with a fiducial die

Abstract: A wafer level fan-out package with a fiducial die is disclosed and may include a semiconductor die and a transparent fiducial die both encapsulated in a molding compound resin, passivation layers on an upper surface and a lower surface of the molding compound resin except where redistribution layers are formed on upper and lower surfaces of the molding compound resin, and a metal pattern on a lower surface of the transparent fiducial die that is visible through an exposed upper surface of the transparent fiducial die. The pattern may comprise a standard coordinate for forming a through mold via utilizing laser drilling.

Development of chip-on-chip with face to face technology as a low cost alternative for 3D packaging

Abstract: This paper describes the ongoing research and development at Amkor Technology of Chip-on-chip/Face to Face (CoC/F2F) technology being developed in parallel with Through Silicon Via (TSV) package assembly. Unlike other 3D packaging techniques using TSVs that require front end processing, CoC/F2F technology uses existing chip attach (C/A) or thermal compression (TC) equipment to connect each die - referred to as the mother die and daughter die for the larger and smaller ICs, respectively. The cost to assemble CoC/F2F is relatively inexpensive, making it an attractive alternative to TSV for many applications. Some of these include the integration of ASIC with logic, MEMS with ASIC, microcontroller with memory, and optoelectronic module with microcontroller.

Metal mesh lid MEMS package and method

Abstract: A metal mesh lid MEMS package includes a substrate, a MEMS electronic component coupled to the substrate, and a metal mesh lid coupled to the substrate with a lid adhesive. The metal mesh lid includes a polymeric lid body having a top port formed therein and a metal mesh cap coupled to the lid body. The metal mesh cap covers the top port and serves as both a particulate filter and a continuous conductive shield for EMI/RF interferences. Further, the metal mesh cap provides a locking feature for the lid adhesive to maximize the attach strength of the metal mesh lid to the substrate.

Semiconductor device using emc wafer support system and fabricating method thereof

Abstract: Provided are a semiconductor device using, for example, an epoxy molding compound (EMC) wafer support system and a fabricating method thereof, which can, for example, adjust a thickness of the overall package in a final stage of completing the device while shortening a fabricating process and considerably reducing the fabrication cost. An example semiconductor device may comprise a first semiconductor die that comprises a bond pad and a through silicon via (TSV) connected to the bond pad; an interposer comprising a redistribution layer connected to the bond pad or the TSV and formed on the first semiconductor die, a second semiconductor die connected to the redistribution layer of the interposer and positioned on the interposer; an encapsulation unit encapsulating the second semiconductor die, and a solder ball connected to the bond pad or the TSV of the first semiconductor die.

Through via connected backside embedded circuit features structure and method

Abstract: A method includes forming through vias in a substrate of an array. Nubs of the through vias are exposed from a backside surface of the substrate. A backside passivation layer is applied to enclose the nubs. Laser-ablated artifacts are formed in the backside passivation layer to expose the nubs. Circuit features are formed within the laser-ablated artifacts. By forming the circuit features within the laser-ablated artifacts in the backside passivation layer, the cost of fabricating the array is minimized. More particularly, the number of operations to form the embedded circuit features is minimized thus minimizing fabrication cost of the array.

Semiconductor device with plated pillars and leads

Abstract: A semiconductor device with plated pillars and leads is disclosed and may include a semiconductor die comprising a conductive pillar, a conductive lead electrically coupled to the conductive pillar, a metal plating layer covering the conductive lead and conductive pillar, and an encapsulant material encapsulating the semiconductor die and at least a portion of the plating layer. The pillar, lead, and plating layer may comprise copper, for example. The plating layer may fill a gap between the pillar and the lead. A portion of the metal plating layer may, for example, comprise an external lead. The metal plating layer may cover a side surface of the pillar and a top surface, side surface, and at least a portion of a bottom surface of the lead. The metal plating layer may cover side and bottom surfaces of the pillar and top, side, and at least a portion of bottom surfaces of the conductive lead.

Ultra large System-in-Package (SiP) module and novel packaging solution for networking applications

Abstract: With increasing data traffic requirements to support mobile devices, tablets and computers, the need for faster internet traffic is mushrooming. The routers and switches used to drive network traffic need to deliver high bandwidth and speed. Key to achieving this high speed and bandwidth is ensuring closer integration between the Application Specific Processors (ASICs) and Memory devices. Consequently, it is important to place memories as close as possible to ASICs. Standard Printed Circuit Board (PCB) design rules make it difficult to place several memories very close to ASICs, and PCBs are already densely populated. Consequently, there are two prevailing technologies that are used to increase density: Through Silicon Vias (TSVs) or System-in-Package (SiP) modules. TSVs are still in early stages of development, whereas smaller SiP modules have already been used in Networking [1, 2]. In this study, we outline an innovative SiP module solution: Implementation of a very large (90 × 90 mm) SiP module with 14 packaged DDR3 memories and 1 large flip low K chip ASIC mounted on a common Ball Grid Array (BGA) substrate. This is likely the largest organic BGA module ever built. Finite Element Analysis was performed to estimate the optimal stiffener and lid parameters for minimal warpage. Complete substrates were assembled with key metrics measured at each step of the assembly process. Excellent coplanarity was achieved in the assembly process. The SiP modules were then mounted on PCBs and the board level assembly process characterized. The modules were successfully mounted on the PCBs. The procedures and key learnings from this evaluation will be outlined in this study.

Semicondutor device with through-silicon via-less deep wells

Abstract: Methods and systems for a semiconductor device with through-silicon via-less deep wells are disclosed and may include forming a mask pattern on a silicon carrier, etching wells in the silicon carrier, and forming metal contacts in the etched wells, wherein the metal contacts comprise a plurality of deposited metal layers. Redistribution layers may be formed on a subset of the contacts and a dielectric layer may be formed on the silicon carrier and formed redistribution layers. Vias may be formed through the dielectric layer to a second subset of the contacts and second redistribution layers may be formed on the dielectric layer. A semiconductor die may be electrically coupled to the second formed redistribution layers and formed vias. The semiconductor die and top surface of the dielectric layer may be encapsulated and the silicon carrier may be thinned to a thickness of the contacts or may be completely removed.

Semiconductor package with improved redistribution layer design and fabricating method thereof

Abstract: A semiconductor package with improved redistribution layer design and fabricating method thereof are disclosed and may include a semiconductor die comprising bond pads, a first redistribution layer (RDL) formed on the semiconductor die. The first RDL has a first end coupled to a bond pad and a second end coupled to a solder bump via under bump metal layers. A second RDL is formed in a same plane of the semiconductor die as the first RDL and is electrically isolated from the first RDL. A first end of the second RDL may be coupled to a bond pad and the second RDL may pass underneath, but be electrically isolated from, the solder bump. A passivation layer may be formed on the first and second RDLs exposing the second end of the first RDL. The under bump metal layers may be formed on the second end of the first RDL exposed by the passivation layer.

Electromigration reliability and current carrying capacity of various WLCSP interconnect structures

Abstract: Wafer Level Chip Scale Packages (WLCSPs) are increasingly being used in Power Management IC (PMIC) applications. Since these packages are typically of small size and low I/O count, the current per bump can be very high for these applications. Therefore, it is important to characterize the electromigration (EM) behavior of WLCSP interconnects to estimate their current carrying capacity. This paper provides an EM performance comparison of four (4) different WLCSP interconnects tested under the same condition. The configurations included: i) Ti/Cu/2.0 μm Ni UBM on 4μm Cu RDL, ii) Ti/Cu/8.6μm Cu UBM on 4μm Cu RDL, iii) Bump-on-trace with 9μm thick Cu RDL, and iv) Bump-on-trace with 14μm thick Cu RDL. A specially designed test vehicle with multiple EM test structures was used for this purpose. The packages were mounted on printed wiring boards (PWB) with either Cu/OSP or NiAu pad surface finish. These assemblies were then tested in a dedicated EM test system using 1.0Amp/161°C as the test condition. More than 4000 hours of testing have been completed so far. Clear differences between these WLCSP interconnects were observed in terms of EM performance. Samples were also removed at different times throughout the test so that detailed SEM analyses could be performed to understand and quantify the failure mode and progression of EM damage for each configuration. The EM performance is found to be significantly better for structures with a 2.0μm Ni UBM layer and the bump-on-trace structure with 14μm thick RDL with no failures so far. However, units with either 8.6μm thick Cu UBM structure or 9μm thick RDL bump-on-trace structure have resulted in a number of failures and at least 2X lower reliability compared to the other two structures. Further, PWB surface finish has a significant effect on EM performance with Cu/OSP performing better than NiAu finish.

Method of forming a thin substrate chip scale package device and structure

Abstract: In one embodiment, a method for forming an electronic package structure includes providing a single unit leadframe having first terminals on a first or top surface. An electronic device is attached to the single unit leadframe and electrically connected to the first terminals. The leadframe, first terminals, and the electronic device are encapsulated with an encapsulating material. Second terminals are then formed by removing portions of a second or bottom surface of the leadframe. In one embodiment, the method can be used to fabricate a thin substrate chip scale package (“tsCSP”) type structure.

Lead frame package and method for manufacturing the same

Abstract: In one embodiment, a lead frame package structure includes a lead frame having sides that surround a die paddle and on which a plurality of leads are formed. An electronic chip is attached to the die paddle and a case is attached to the lead frame to seal the leads and the electronic chip. One or more discharge holes are formed on and extending through one or more specific leads and/or on and extending through a predetermined position of the die paddle. The discharge holes are configured to discharge air pressure that forms during the assembly process thereby improving the reliability of the packaged electronic chip.

The Study of the Polydispersivity Effect on the Thermal Conductivity of Particulate Thermal Interface Materials by Finite Element Method

Abstract: Thermal interface materials (TIMs) are particulate composite materials widely used in the microelectronics industry to reduce the thermal resistance between the device and the heat sink. Predictive modeling using fundamental physical principles is critical to developing new TIMs, since it can be used to quantify the effect of polydispersivity, volume fraction and arrangements on the effective thermal conductivity. A random network model that can efficiently capture the near-percolation transport in these particle-filled systems was developed by the authors, which can take into account the interparticle interactions and random size distributions. In this paper, a Java-based code is used to generate the microstructures at different volume fraction and different particle-size distribution (PSD). COMSOL was used to investigate the impact of polydispersivity on the effective thermal conductivity of particulate TIMs. The log-normal distribution was used to capture the filler PSD. From the simulation results, there exists an optimum value of the polydispersivity which has the largest thermal conductivity for a given volume fraction.

Apparatus and method for testing sound transducers

Abstract: In one embodiment, an apparatus for testing sound transducers includes a test socket having at least one acoustic generator and at least one sound monitoring device integrated therein. In one embodiment, the test socket includes a well for holding the sound transducer during test, the well being in communication with the at least one acoustic generator and the at least one sound receiving device.

Robust pillar structure for semicondcutor device contacts

Abstract: Methods and systems for a robust pillar structure for a semiconductor device contacts are disclosed, and may include processing a semiconductor wafer comprising one or more metal pads, wherein the processing may comprise: forming a second metal contact on the one or more metal pads; forming a pillar on the second metal contact, and forming a solder bump on the second metal contact and the pillar, wherein the pillar extends into the solder bump. The second metal contact may comprise a stepped mushroom shaped bump, a sloped mushroom shaped bump, a cylindrical post, and/or a redistribution layer. The semiconductor wafer may comprise silicon. A solder brace layer may be formed around the second metal contact. The second metal contact may be tapered down to a smaller area at the one or more metal pads on the semiconductor wafer. A seed layer may be formed between the second metal contact and the one or more metal pads on the semiconductor wafer. The pillar may comprise copper.

Electronic device package structure and method fabricating the same

Abstract: In one embodiment, an electronic device package structure includes an electronic die having conductive pads on one surface. The one surface is further attached to at least one lead. A conductive layer covers at least one conductive pad and at least portion of the lead thereby electrically connecting the lead to the conductive pad.

Microfluidics sensor package fabrication method and structure

Abstract: A microfluidics sensor package includes a microfluidics sensor die having an active surface, bond pads on the active surface, and an active area on the active surface. A standoff pattern is formed on the active surface to extend to a precise height above the active surface. A lid is mounted to the standoff pattern by a lid adhesive. By using the standoff pattern to precisely space the lid above the active surface, a microfluidics cavity between the lid and the active surface is precisely created allowing for precise control of fluid flowing through the microfluidics cavity. By precisely controlling the flow of fluid through the microfluidics cavity, accurate results, e.g., of the laboratory functions performed on the fluid, are provided.

The reliability performance of copper wire bonding BGA package by way of HAST methodology

Abstract: Cu wire bonding technology is increasingly being used for the various IC packages from consumer application to high-reliability electronic products due to cost reduction consideration as well as electrical and thermal performance improvement in comparison with Au wire bonding. Despite these positive impacts of the improvements, the reliability still needs to be correctly assessed by the industry in a quantitative manner due to uncertain materials and assembly process issue. In the study, multiple Cu wire types and wire bonding process conditions are designed to validate assembly integrity based on Lead free BGA package with 14×14 body size and 384 I/O. Two bonding wire manufacturers provide the copper wire and palladium coated copper wire used for evaluation. Green molding compound free of halogenated flame retardant with known chloride content is used to mold the BGA package. After process characterization is verified based on wire pull and bond shear test. A HAST methodology (Highly Accelerated Stress Test) is applied to validate the BGA package reliability for the understanding of corresponding materials interaction among the wire material, molding compound and bonding pad metallization due to the acceleration stress drive from the temperature and humidity and bias voltage. In this task, there are five HAST conditions executed including 130°C/85RH%, 130°C/55RH%, 110°C/85RH%, 120°C/60RH% and 85°C/85RH% under 5.5 volt bias. Various temperature and humidity represent relative stress factors to accelerate the test to fail, as well the 3 stress factors usually influence the ionic ingredient in the molding compound to react with Cu wire and pad metallization. There are 4 daisy chain loops designed to monitor electrical resistance after each time period set in one BGA package for the failure judgment when resistance is fully open. Base on the HAST result and following failure analysis, the effect of testing duration, temperature and humidity differences and mold compound type are discussed.

Embedded die in panel method and structure

Abstract: Methods for an embedded die panel are disclosed and may include fabricating a first layered structure by: forming first redistribution layers on a first carrier, forming a first dielectric layer on the first redistribution layers and carrier, forming a mask pattern on the first dielectric layer exposing a portion of the first dielectric layer, forming a second dielectric layer on the exposed portion of the first dielectric layer, forming vias in the first and second dielectric layers, and forming second redistribution layers on the second dielectric layer. The mask pattern may be removed forming a die cavity defined by the second dielectric layer. A second layered structure coupled to the first layered structure may be formed comprising a second carrier, a third dielectric layer, third and fourth redistribution layers on opposite surfaces of the third dielectric layer, and a semiconductor die.

An Improved Efficient Network Model for Determining the Effective Thermal Conductivity of Particulate Thermal Interface Materials

Abstract: Thermal interface materials (TIMs) are particulate composite materials widely used in the microelectronics industry to reduce the thermal resistance between the device and heat sink. Predictive modeling using fundamental physical principles is critical to developing new TIMs since it can be used to quantify the effect of particle volume fraction and arrangements on the effective thermal conductivity. The existing analytical descriptions of thermal transport in particulate systems do not accurately account for the effect of interparticle interactions, especially in the intermediate volume fractions of 30–80%. An efficient random network model (RNM) that captures the near-percolation transport in these particle-filled systems, taking into account the interparticle interactions and random size distributions, was previously developed by Kanuparthi et al. The RNM approach uses a cylindrical region to approximate the thermal transport within the filler particles and to capture the interparticle interactions. However, this approximation is less accurate when the polydispersivity of the particulate system increases. In addition, the accuracy of the RNM is dependent on the parameters inherent in an analytical description of thermal transport between two spherical particles and their numerical approximation into the network model. In the current paper, a novel semispherical approximation to the conductance of the fillers is presented as an alternative to the cylindrical region approximation used earlier. Compared with the cylindrical model, the thermal conductivities of the semispherical model are more closely to the finite element (FE) results. Based on the FE analysis, the network model is improved by developing an approximation of the critical cylindrical region between two spherical particles over which energy is transported. Comparing the RNM results with FE results and experimental data, a linear relationship of the critical parameter with the thermal conductivity ratio and the volume fraction was found that provides a more accurate prediction of the effective thermal conductivity of the particulate TIMs.

Warpage Characterization and Improvements for IC Packages with Coreless Substrate

Abstract: Coreless package substrates are preferred for their superior electrical performance and thin profile compare to conventional substrates with core. However, one of the major concerns with coreless substrate packages is warpage control. It is difficult to meet industry standards for co-planarity because of the high CTE of the coreless substrates and the missing stiff core material in the stack up of the coreless structure. Finite element analysis (FEA) is utilized to investigate the use of coreless substrate in different package configurations. In this study, known stiffening structures such as a stiffener ring, lid and molding options are investigated to characterize the advantages and disadvantages of using each of these structures to control the warpage in an IC package with coreless substrate. Available shadow moire data is used for initial correlation of the finite element model and further design changes were carried out to stiffen the structure in the final packaged configuration. It is important to ...

Electronic package structure with insulated adhesion portion for affixing and isolating lands spaced apart from land connect bar within a leadframe

Abstract: In one embodiment, a semiconductor device includes a leadframe structure. A semiconductor die is attached to a die pad. Land connect bars are spaced apart from the die pad and a plurality of lands are between the land connect bars and the die pad and are spaced apart therefrom. Insulation members are adhered to the land connect bars and the plurality of lands to hold the land connect bars and the plurality of lands together and to electrically isolate them. An encapsulant covers the semiconductor die and at least portions of the plurality of lands, the die pad, and the land connect bars and further fills spaces between the land connect bars and the plurality of lands.

Flip chip assembly with advanced RDL technology

Abstract: With silicon node technology shrinking to beyond 14nm, die pad pitch becomes smaller and bumps become finer dimensioned so that I/O pads can be laid out. In many cases, flip chip assembly is required because of layout considerations, performance, and cost effectiveness. Often, the fine pitch layout poses great challenges to existing bumping and flip chip assembly capability. This paper is to report an advanced redistribution layer (RDL) solution for a tighter pitch designed die so that that current flip chip assembly process can be used. The test vehicle die has two rows of staggered 40/80um pitch peripheral pads. The RDL is constructed with PBO-Cu-PBO stack and an advanced 10/10um L/S RDL design rule. After the RDL application, the bump pitch of the die is expanded into an area array flip chip type with 170um pitch. Mechanical, Electrical, Constructional analysis is reported in the paper. Assembly process and manufacturability with thermal compression flip chip technology is evaluated. Initial construction analysis and reliability test is conducted. The results clearly show that this RDL technology is feasible and potentially a viable choice for new Silicon node technology die with tight pitch.

Embedded vibration management system

Abstract: Methods for an embedded vibration management system are disclosed and may include fabricating a semiconductor package that supports vibration management by forming an array of vibration absorbing structures, placing the array proximate to a leadframe comprising two-legged supported leads, placing a semiconductor device above the leadframe, and encapsulating the semiconductor device and the leadframe. Each vibration absorbing structure may comprise a mass element formed on a material with lower density than that of the mass element. The array may be placed on a top, a bottom, or both surfaces of the leadframe. Sections of the array may be placed symmetrically with respect to the semiconductor device. The vibration absorbing structures may be cubic in shape and may be enclosed in an encapsulating material. The two-legged supported leads may be formed by bending metal strips with holes. The vibration absorbing structures may be exposed to the exterior of the semiconductor package.

Plating Structure For Wafer Level Packages

Abstract: A plating structure for wafer level packages are disclosed and may include a semiconductor wafer comprising a plurality of semiconductor die and a plating structure for forming an under bump metal on redistribution layers on the plurality of semiconductor die. The plating structure may comprise a plating connection line around a periphery of the semiconductor wafer, and a plating bar coupling the plating connection line to plating traces on the plurality of semiconductor die. The plating traces may be electrically coupled to the redistribution layers on the plurality of semiconductor die. The semiconductor wafer may comprise a reconstituted wafer of said semiconductor die. The semiconductor wafer may comprise a wafer prior to singulating the plurality of semiconductor die. The plating bar may be located in a sawing line for the singulating of the plurality of semiconductor die. A passivation layer may cover the redistribution layer and the plating traces.

Fine pitch PoP introduction

Abstract: Package-on-package (PoP) has been widely adopted for 3D integration of logic and memory within mobile handsets and other portable multimedia devices. Typical PoP solution is applied to logic processor as bottom package and memory device as top package. TMV® solution is being applied to reduce the warpage and achieve the fine pitch PoP and stable stacking performance. Currently, 0.4mm MIF(Memory Interface Pitch) is the minimum pitch under production and more fine MIF pitch is being requested because more functions are being integrated on chip then chip size becomes larger even wafer node is going narrower. To sustain the similar package size with larger chip size, fine pitch PoP is required. In this paper, 0.3 and 0.27mm MIF pitch PoP will be studied as a solution for fine pitch PoP and as a interface material between Top and Bottom package, solder ball and Cu post will be evaluated.

Innovative 3D Structures Utilizing Wafer Level Fan-Out (WLFO) Technology

Abstract: The tremendous growth in the mobile handset, tablet, and networking markets has been fueled by consumer demand for increased mobility, functionality, and ease of use. This, in turn, has been driving an increase in functional convergence and 3D integration of IC devices, resulting in the need for more complex and sophisticated packaging techniques. A variety of advanced IC interconnect technologies are addressing this growing need, such as Thru Silicon Via (TSV), Chip-on Chip (CoC), and Package-on-Package (PoP). In particular, the emerging Wafer Level Fan-Out (WLFO) technology provides unique and innovative extensions into the 3D packaging realm. Wafer Level Fan-Out is a package technology designed to provide increased I/O density within a reduced footprint and profile for low density single & multi-die applications at a lower cost. The improved design capability of WLFO is due, in part, to the fine feature capabilities associated with wafer level packaging. This can allow much more aggressive design rules...