Showing papers by "Amkor Technology published in 2020"

Heterogeneous Integration Using Organic Interposer Technology

Abstract: As the costs of advanced node silicon have risen sharply with the 7 and 5-nanometer nodes, advanced packaging is coming to a crossroad where it is no longer fiscally prudent to pack all desired functionality into a single die. While single-die packages will still be around, the high-end market is shifting towards multiple-die packages to reduce overall costs and improve functionality. This shift is not just to add local memory, such as the addition of high-bandwidth memory (HBM) module(s) to an application-specific integrated circuit (ASIC) die, but also to separate what would have been a monolithic ASIC in prior generations to its constituent parts, such as the central processing unit (CPU) cores, serializer/deserializer (SerDes) and input/output (I/O) blocks. By splitting the monolithic die into smaller functional blocks, costs can be reduced through improved wafer yield on the smaller CPU cores and re-using older, vetted intellectual property (IP) from a prior silicon node for the I/O and SerDes that do not necessarily need the most advanced silicon node.The traditional approach to fine-pitch multi-die packaging has been silicon interposers with Through Silicon Vias (TSVs). While the TSV approach has ushered in new performance levels never seen before, one of the major limitations is the inability to scale with higher and higher frequencies. The maximum frequency that a silicon interposer can handle between die-to-die interconnects is approximately 4 GHz due to the parasitics of the silicon. As dieto-die interconnects increase their bandwidth to higher and higher levels, the 4-6 GHz limitation can become a major bottleneck. Eliminating the silicon and silicon dioxide dielectrics and using polymers as the dielectric and the interposer itself can solve this problem.This paper will discuss how to use High-Density Fan-Out (HDFO) technology to replace the TSV-bearing silicon interposer with an organic interposer to enable higher bandwidth die-to-die interconnects for heterogeneous integration.

High-Performance Flip Chip Bonding Mechanism Study with Laser Assisted Bonding

Abstract: Recent advanced flip chip ball grid array (FCBGA) packages require high input/output (I/O) counts, fine-pitch bumps and large/thin package substrates. One of the key hurdles to accommodate these requirements is the flip chip bonding process. Therefore, advanced flip chip bonding technologies are continuously being developed and one of the promising solutions is laser assisted bonding (LAB) technology. The key advantage of LAB is its extremely short bonding time (less than 1 sec) with a localized heating area which provides low thermal and mechanical stresses.In this study, two bonding profiles of "time fixed" and "power fixed" are tested using 15.2 x 15-mm2 FCBGA test vehicles with three difference die thicknesses. Wetting sequences of the solder joints are inspected with time interval of 100 ms. Solder bump interconnections are analyzed by cross section and reliability tests are performed. LAB is also compared with thermocompression bonding (TCB) for process and solder joint characteristics.

Effect of Electromigration-Induced Joule Heating on the Reliability of Sn-Ag Microbump with Different UBM Structures

Abstract: The effect of current stress-induced Joule heating on two different under-bump metallization (UBM) structures in Sn-Ag microbumps was investigated with current stressing at 150°C and a current density of 5 &!thinsp;× 104 A/cm2. Both Ni UBM and Cu UBM configuration microbump structures underwent extensive electromigration (EM) testing, with results revealing a longer lifetime with the Cu UBM configuration than the Ni UBM structure. The observed EM failure mechanism in the Ni UBM configuration was identified as a void formation within the bump interconnected Al trace and not due to damage accumulation inside the microbump structure. The intermetallic compound developed inside the microbump was formed and maintained its stability throughout the current stressing period. To identify the main driving force of damage accumulation in the Al trace, the current density and temperature distributions in the Sn-Ag microbumps were analyzed numerically via the finite element method. The simulation results showed higher Joule heating with the Ni UBM than the Cu UBM microbump configuration, along with the bump geometrical contribution of add-on higher Joule heating in the Ni UBM microbump structure.

Wafer Level Void-Free Molded Underfill for High-Density Fan-out Packages

Abstract: In this study, experiments and mold flow simulation results are presented for a void-free wafer level molded underfill (WLMUF) process with High-Density Fan-Out (HDFO) test vehicles using a wafer-level compression molding process The redistribution layer (RDL)-first technology was applied with 3 layers of a fine-pitch RDL structure The test samples comprised $115 \times 125-\text{mm}^{2}$ die with tall copper (Cu) pillars around the die Destructive analysis was used to clearly inspect MUF voids on the whole wafer area The molded wafer was ground to the bump area where the MUF voids exist using a mold grinding machine and MUF voids were inspected through a high-resolution scope The WLMUF characteristics of the conventional compression molding process with various epoxy molding compound (EMC) types have been investigated A void-free WLMUF process was achieved by applying an optimized EMC dispensing method and parameters These results are verified through the mold flow simulation, which correlated to the experimental results Finally, the void-free WLMUF HDFO samples passed reliability tests of temperature cycling (TC), high temperature storage (HTS) and Unbiased Highly Accelerated Stress Test (UHAST) after moisture resistance test (MRT) Level 3

A New RDL-First PoP Fan-Out Wafer-Level Package Process with Chip-to-Wafer Bonding Technology

Abstract: Fan-Out Wafer-Level Interposer Package-on-Package (PoP) design has many advantages for mobile applications such as low power consumption, short signal path, small form factor and heterogeneous integration for multi-functions. In addition, it can be applied in various package platforms, including PoP, System-in-Package (SiP) and Chip Scale Package (CSP). These advantages come from advanced interconnection technology called a redistribution layer (RDL).However, a PoP-type RDL-base platform requires dual-side RDLs on both top and bottom sides to stack another package on top. In a monolithic process flow, that means the second RDL only can be fabricated after finishing all the first RDL and the assembly processes such as flip-chip bonding, molding and grinding. Therefore, this process flow is not quite as advantageous as a non-PoP type platform because chips can be lost during the second RDL process.In this paper, to address this RDL-base Interposer PoP challenge, a real chip-last process flow with a chip-to-wafer (C2W) bonding technology is introduced. And the results are presented of building and testing an RDL-base wafer-level Interposer PoP with a size of 12.5 x 12.5 mm2 and thickness of 0.357 mm including solder ball. The bottom side has a 3-layer RDL structure and the top RDL for the package stacking has a 1-layer structure. These RDLs are implemented with copper (Cu) lines with 5 μm/10 μm of line & space (L/S) and copper (Cu) cored solder balls (CCSBs) are used as the vertical interconnect components. The silicon die and CCSBs’ joint quality is confirmed by reliability testing. The test vehicle package passed all the reliability tests of moisture resistance test (MRT) L3, Temperature Cycle, Condition B (TCB) 1,000 cycles and high temperature storage (HTS) 1,000 hrs.

Volume Shrinkage-Induced Voiding Mechanism During Electromigration of Cu/Ni/Sn-Ag Microbump.

Abstract: The effects of annealing, electromigration, and thermomigration on volume shrinkage and voiding mechanisms of Cu/Ni/Sn-2.5Ag microbumps are systematically investigated by using in-situ scanning electron microscopy under current stressing of 1.5×105 A/cm² at 150 °C. The resistance increases rapidly in the initial stage due to formation of intermetallic compounds (IMC)s followed by a gradual increase in resistance. Growth of Ni₃Sn₄ IMCs is controlled by a diffusion-dominant mechanism, and voids and volume shrinkage are closely related to IMC phase transformation of (Au, Ni)Sn₄ to Ni₃Sn₄ in microbumps.

Development of an Extremely High Thermal Conductivity TIM for Large Electronics Packages in the 4 th Industrial Revolution Era

Abstract: The capability and diversity of high-performance microprocessors is increasing with each process technology generation to meet increasing application demands. The cooling designs for these chips must deal with larger temperature gradients across the die than previous generations. Dissipation of the thermal energy from heat generating parts to a heat sink via conduction occurs through a thermal interfacial material (TIM). One of the most important parameters of TIMs is their thermal conductivity that impacts the efficiency of the thermal management. Therefore, in this study, three new different types of TIMs with high thermal conductivity (> 20W/mK) were examined.In this paper, workability and reliability test results will be shown for metal sheet TIM (60W/mK), graphite sheet TIM (24W/mK) and silver (Ag) sintered TIM (50W/mK) materials. All test package sizes are covered with 52.5-mm body size or 45-mm body size for large package with > 45-mm body size in a flip chip ball grid array (FCBGA) package. The reliability test items are high-temperature storage (HTS) @ 150’C 1000hrs, temperature cycling (TC) ‘B’ 1000X and unbiased highly accelerated stress test (uHAST) for 96hrs. Open/short (O/S) test, scanning acoustic tomography (SAT) or X-ray analysis data are reported. Post reliability test, lid pull test results will be shown as well.

Effects of Post-annealing and Co Interlayer Between SiN x and Cu on the Interfacial Adhesion Energy for Advanced Cu Interconnections

Abstract: Effects of Co interlayer and 200 °C post-annealing treatment on interfacial adhesion energy of SiNx/Cu structure were systematically investigated. Initial interfacial adhesion energy of SiNx/Cu structure measured by double cantilever beam test was 0.92 J/m2. The interfacial adhesion energy increased to 2.94 J/m2 with Co interlayer between SiNx and Cu films. After post-annealing treatment at 200 °C for 500 h, the interfacial adhesion energy of SiNx/Co/Cu structure decreased to 0.95 J/m2. X-ray photoelectron spectroscopy analysis revealed that the interfacial adhesion energy increased for SiNx/Co/Cu thin films due to CoSi2 reaction layer at SiNx/Co interface, but sharply decreased during post-annealing treatment by SiO2 formation at SiNx/Co interface.

Development of a Mobile Robot with Camera-based Target Tracking and Obstacle Avoidance Systems

Abstract: This work describes the preliminary design and development of a mobile robot called CREC (Camera-Based Mobile Robot for Elderly Care). The robot uses a low-cost HC-SR04 ultrasonic sensor to avoid obstacle, and a Pixy CMUcam5 camera as the vision-based sensor to track the target. This camera uses colour marker tag to follow and monitor the target. CREC uses an Arduino UNO microcontroller to fuse data conveyed by the ultrasonic sensor and camera so that the robot can follow the target and avoid obstacles simultaneously. In this work, the hardware design of CREC is described. Furthermore, preliminary experiments to characterize the ultrasonic sensor and Pixy camera are demonstrated to verify the usefulness of the selected sensors for the mobile robot.

Hybrid 3D Package with RDL and Laminate Substrate for Ultra-Thin and High-Bandwidth Applications

Abstract: In this work, a hybrid 3D package combining a redistribution layer (RDL) and laminate substrate layer for ultra-thin and high-bandwidth mobile applications are discussed and demonstrated. The motivation behind this hybrid 3D package structure was leveraging the advantages of high density RDL layer and advanced laminate substrate layer in one package to optimize package features or performance in bandwidth, package height, assembly manufacturing and package level as well as board level reliability to each specific industry requirement. For demonstration purposes, a $12.5\times 12.5-\text{mm}$ hybrid 3D packages combining a high density RDL and advanced laminate-substrate layer were designed and manufactured. In this demonstration, the $12.5\times 12.5-\text{mm}$ hybrid 3D package showed $395\ \mu \mathrm{m}$ package height including ball grid array (BGA) solder ball height and package warpage of $+64\ \mu \mathrm{m}$ (in crying mode) at 25°C and $-81\ \mu \mathrm{m}$ (in smile mode) at 260°C. The demonstration package passed package level reliability tests including unbiased highly accelerated stress test (uHAST), temperature cycling (TC) test and high temperature storage (HTS) test. The package showed less creep strain energy density (CSED) of the BGA solder balls under board level reliability-temperature cycling conditions than that of the RDL-based 3D package in the finite element model (FEM) simulation to a fully top package and 3D package stacked structure.

Semiconductor device with improved thermal dissipation and manufacturing methods

Abstract: A semiconductor device includes a semiconductor die, a redistribution structure, a interconnection structure, and a thermal path structure. The redistribution structure includes an insulation layer over a first surface of the semiconductor die and a conductive trace separated from the first surface by the insulation layer. The conductive trace extends laterally over the first surface from a first end toward a second end that is electrically coupled to a bond pad on the first surface of the semiconductor die. The interconnection structure is coupled to the first end of the conductive trace. The thermal path structure provides a thermal path between the semiconductor die and the interconnection structure. In some embodiment, the thermal path structure comprises a thermal pad that passes through the insulation layer. In other embodiments, the thermal path structure comprises a dummy pad on the first surface of the semiconductor die.

Semiconductor device and method of manufacturing a semiconductor device

Abstract: The invention discloses a semiconductor device and a method of manufacturing a semiconductor device The semiconductor device comprises a substrate having a substrate top side, a substrate lateral side, and a substrate bottom side, an electronic device on the substrate top side, and an encapsulant on the substrate top side and contacting a lateral surface of the electronic device The substrate comprises a conductive structure and a dielectric structure that extends comprising a protrusion in contact with the encapsulant The conductive structure comprises a lead comprising a lead flank, the lead flank comprising a cavity and a conductive coating on a surface of the lead in the cavity The conductive structure comprises a pad exposed at the substrate top side, embedded in the dielectric structure, and adjacent to the protrusion, to electrically couple with the electronic device via a first internal interconnect Other examples and related methods are also disclosed herein

Sensor package and manufacturing method thereof

Abstract: A fingerprint sensor device and a method of making a fingerprint sensor device. As non-limiting examples, various aspects of this disclosure provide various fingerprint sensor devices, and methods of manufacturing thereof, that comprise an interconnection structure, for example a bond wire, at least a portion of which extends into a dielectric layer utilized to mount a plate, and/or that comprise an interconnection structure that extends upward from the semiconductor die at a location that is laterally offset from the plate.

Semiconductor package using cavity substrate and manufacturing methods

Abstract: A semiconductor package includes a cavity substrate, a semiconductor die, and an encapsulant. The cavity substrate includes a redistribution structure and a cavity layer on an upper surface of the redistribution structure. The redistribution structure includes pads on the upper surface, a lower surface, and sidewalls adjacent the upper surface and the lower surface. The cavity layer includes an upper surface, a lower surface, sidewalls adjacent the upper surface and the lower surface, and a cavity that exposes pads of the redistribution structure. The semiconductor die is positioned in the cavity. The semiconductor die includes a first surface, a second surface, sidewalls adjacent the first surface and the second surface, and attachment structures that are operatively coupled to the exposed pads. The encapsulant encapsulates the semiconductor die in the cavity and covers sidewalls of the redistribution structure.

Semiconductor devices with shield

Abstract: A semiconductor device includes a lead frame, an electronic device, a package body, and a first shield plate. The lead frame includes a die mount structure, signal leads, a first shield lead, a second shield lead, and a first shield mount that spans the first and second shield leads. The electronic device can be mounted to the die mount structure and can be coupled to the signal leads. The package body encapsulates the electronic device and the lead frame such that (i) each of the first shield lead, the second shield lead, and the signal leads includes an external portion that extends beyond the exterior surface of the package body, and (ii) the first shield mount extends beyond the exterior surface of the package body. The first shield plate can be coupled to the first shield mount.

Semiconductor devices and related methods

Abstract: In one example, a semiconductor device can comprise a substrate, a device stack, first and second internal interconnects, and an encapsulant. The substrate can comprise a first and second substrate sides opposite each other, a substrate outer sidewall between the first substrate side and the second substrate side, and a substrate inner sidewall defining a cavity between the first substrate side and the second substrate side. The device stack can be in the cavity and can comprise a first electronic device, and a second electronic device stacked on the first electronic device. The first internal interconnect can be coupled to the substrate and the device stack. The second internal interconnect can be coupled to the second electronic device and the first electronic device. The encapsulant can cover the substrate inner sidewall and the device stack, and can fill the cavity. Other examples and related methods are disclosed herein.

Stiffener package and method of fabricating stiffener package

Abstract: A wafer level fan out package includes a semiconductor die having a first surface, a second surface, and a third surface. A stiffener is disposed on the third surface of the semiconductor die. A conductive via passes through the stiffener. First and second electrically conductive patterns electrically connected to the conductive via are disposed on the first and second surfaces of the semiconductor die and stiffener. Solder balls are electrically connected to the first or second electrically conductive patterns.

Virtual Prototyping, Design for Reliability, and Qualification for a Full SiP Product Portfolio of a FOWLP Line

Abstract: Low-Density Fan-Out (LDFO) (or Fan-out wafer-level-packaging) is a very popular technology for creating Systems in Package (SiP) designs. However, in reliability tests and in field use, cracks in the copper pads, in the redistribution layer (RDL) and in the solder balls are significant failure modes. To improve the package reliability, these risks need to be assessed during the design of the new products. This paper describes the architecture, the validation and the implementation of a numerical scheme for virtual prototyping, virtual design optimization, and virtual design qualification. The flexibility of the set of parametric finite element models is shown for an entire portfolio of new automotive SiP products in a LDFO fabrication line ranging from single die and multi-die to 3D stacked configurations. In addition, the new schemes are applied to study a novel pad design. Undulations have been introduced to prevent the permanent loss of electrical connection through complete pad cracking. The new modeling technique enables the semi-automated assessment of crack initiation and crack propagation in the copper pads and in the solder balls as well as the effects of delamination of the RDL dielectrics from the die. Experimental findings demonstrate the validity of the simulation results and the design recommendations deduced from them.

Manufacturing method of semiconductor package including laser processing

Abstract: A manufacturing method of a semiconductor package includes locating a plurality of semiconductor packages on a substrate, forming a resin insulating layer covering the plurality of semiconductor devices, forming grooves, in the resin insulating layer, enclosing each of the plurality of semiconductor devices and reaching the substrate, and irradiating the substrate with laser light in positional correspondence with the grooves to separate the plurality of semiconductor devices from each other.

Carrier assisted substrate method of manufacturing an electronic device and electronic device produced thereby

Abstract: An electronic device structure and a method for making an electronic device. As non-limiting examples, various aspects of this disclosure provide a method of manufacturing an electronic device that comprises the utilization of a carrier assisted substrate, and an electronic device manufactured thereby.

Semiconductor device and a method of manufacturing a semiconductor device

Abstract: In one example, a semiconductor package comprises a substrate having a top surface and a bottom surface, an electronic device mounted on the top surface of the substrate and coupled to one or more interconnects on the bottom surface of the substrate, a cover over the electronic device, a casing around a periphery of the cover, and an encapsulant between the cover and the casing and the substrate.