Showing papers by "Yeshwantrao Chavan College of Engineering published in 2016"

Critical success factors for Lean Six Sigma in SMEs (small and medium enterprises)

Abstract: Purpose – The purpose of this paper is to identify and list critical success factors (CSFs) of Lean Six Sigma (LSS) framework affecting and influencing quality, operational and financial performance of small and medium enterprises (SMEs). It also intends to guide researchers and practitioners in selecting appropriate set of CSFs for empirical studies, developing frameworks and to ensure effective implementation experience of LSS. Design/methodology/approach – It systematically reviews literature on CSFs and Indian experience regarding LSS. It uses exploratory approach for data collection and documents various studies depicting both manufacturing and service experiences by using time tested statistical tools to prioritize CSFs, which critically influence LSS implementation. Findings – The study guides and facilitates researchers and practitioners in using the most appropriate set of CSFs for empirical studies and in developing/modifying/reviewing application frameworks. It also guides implementation experi...

Simplified Space Vector Modulation Techniques for Multilevel Inverters

Abstract: This paper presents simplified techniques for the space vector modulation (SVM) of any n -level multilevel inverter. Three techniques have been presented to simplify the identification of the nearest three vectors to the reference vector. The first two techniques are based on resolving the multilevel inverter space vector diagram into appropriate two-level hexagons. This results in simplification of the multilevel SVM problem into a two-level SVM problem. The third technique is an algorithm-based technique which makes use of a 60°-spaced gh coordinate system to perform the SVM of a multilevel inverter. Switching sequence design for all the three techniques is presented with the aim of minimization of the device switching frequency. Simulation and experimental results have been provided to verify the feasibility of the proposed techniques. Simulation results are provided for up to 21-level cascaded H-bridge (CHB) inverters, while the experimental verification is done on a five-level laboratory prototype. Although only the CHB inverter is considered in this study, the proposed techniques are perfectly general and can be applied to all types of multilevel inverters, and are extendable to any number of levels.

Liquid feed passive direct methanol fuel cell: challenges and recent advances

Abstract: This paper provides an overview of technological challenges and recent advances in the liquid feed passive direct methanol fuel cells (DMFC). Important issues viz. species management, thermal management, methanol crossover, sluggish anode kinetics, durability and stability, and cost are discussed in detail. Methanol management, water management, oxygen management, and carbon dioxide management are covered under species management. The present technological status is given and future research directions are suggested.

Question answering system on education acts using NLP techniques

Abstract: Question Answering (QA) system in information retrieval is a task of automatically answering a correct answer to the questions asked by human in natural language using either a pre-structured database or a collection of natural language documents. It presents only the requested information instead of searching full documents like search engine. As information in day to day life is increasing, so to retrieve the exact fragment of information even for a simple query requires large and expensive resources. This is the paper which describes the different methodology and implementation details of question answering system for general language and also proposes the closed domain QA System for handling documents related to education acts sections to retrieve more precise answers using NLP techniques.

Cyber security analysis using vulnerability assessment and penetration testing

Abstract: In last twenty years, use of internet applications, web hacking activities have exaggerated speedily. Organizations facing very significant challenges in securing their web applications from rising cyber threats, as compromise with the protection issues don't seem to be reasonable. Vulnerability Assessment and Penetration Testing (VAPT) techniques help them to go looking out security loopholes. These security loopholes could also be utilized by attackers to launch attacks on technical assets. Thus it is necessary ascertain these vulnerabilities and install security patches. VAPT helps organization to determine whether their security arrangements are working properly. This paper aims to elucidate overview and various techniques used in vulnerability assessment and penetration testing (VAPT). Also focuses on making cyber security awareness and its importance at various level of an organization for adoption of required up to date security measures by the organization to stay protected from various cyber-attacks.

FCM Clustering Algorithms for Segmentation of Brain MR Images

Abstract: The study of brain disorders requires accurate tissue segmentation of magnetic resonance MR brain images which is very important for detecting tumors, edema, and necrotic tissues. Segmentation of brain images, especially into three main tissue types: Cerebrospinal Fluid CSF, Gray Matter GM, and White Matter WM, has important role in computer aided neurosurgery and diagnosis. Brain images mostly contain noise, intensity inhomogeneity, and weak boundaries. Therefore, accurate segmentation of brain images is still a challenging area of research. This paper presents a review of fuzzy c-means FCM clustering algorithms for the segmentation of brain MR images. The review covers the detailed analysis of FCM based algorithms with intensity inhomogeneity correction and noise robustness. Different methods for the modification of standard fuzzy objective function with updating of membership and cluster centroid are also discussed.

Use of Neural Networks in cryptography: A review

Abstract: In cryptography secret information is made unreadable for an unauthorized user. There are many cryptographic algorithms are available, but they are more complex techniques and requires more computational power. This paper gives a review of how Neural Networks contributes a help in cryptography and how neural network and cryptography together can be used for security.

Breast histopathology image segmentation using spatio-colour-texture based graph partition method.

Abstract: This paper proposes a novel integrated spatio-colour-texture based graph partitioning method for segmentation of nuclear arrangement in tubules with a lumen or in solid islands without a lumen from digitized Hematoxylin-Eosin stained breast histology images, in order to automate the process of histology breast image analysis to assist the pathologists. We propose a new similarity based super pixel generation method and integrate it with texton representation to form spatio-colour-texture map of Breast Histology Image. Then a new weighted distance based similarity measure is used for generation of graph and final segmentation using normalized cuts method is obtained. The extensive experiments carried shows that the proposed algorithm can segment nuclear arrangement in normal as well as malignant duct in breast histology tissue image. For evaluation of the proposed method the ground-truth image database of 100 malignant and nonmalignant breast histology images is created with the help of two expert pathologists and the quantitative evaluation of proposed breast histology image segmentation has been performed. It shows that the proposed method outperforms over other methods.

Design and implementation of 64 bit multiplier using vedic algorithm

Abstract: As floating point architecture is very hot topic for researchers so challenges are always there to design the efficient Floating point architecture. Out of other operations, Floating point multiplication is the most commonly used operation and it requires the multiplication of the mantissa of Floating point numbers. This paper presents the highly efficient 64 bit multiplier for the mantissa calculation using rule or sutra of Vedic mathematics called Urdhva Tiryakbhyam Sutra which deals with vertically and crosswise multiplication. Using this sutra in the computation algorithm of DSP processors, can enhance the efficiency and at the same time can reduce the complexity, area, power consumption and delay. Starting from the design of 2 bit Vedic multiplier we went up to design 64 bit Vedic multiplier as presented in this paper. Vedic multiplier is coded in Verilog HDL and targeted to three different families of FPGA Spartan6, Virtex5 and Virtex6 in Xilinx 13.1 ISE software. Result is compared with the Karatsuba, Vedic-Karatsuba and Optimized Vedic multiplier and found 33% reduction in delay.

Distributed power flow controller using single phase DSSC to realize active power flow control through transmission line

Abstract: Day by day electricity demand is increasing more and more. To fulfil this demand, new power stations are installed and they are adding power to the existing grid. Power generated from renewable sources is also adding power to the existing grid. It results in overloading of existing transmission lines. Hence it is an urgent requirement of power flow control of future grid. Flexible AC Transmission System (FACTS) controls power flow through line. Distributed power flow controller is a Distributed-FACTS device which provides cost effective and reliable power flow control through existing transmission line. This paper presents distributed static series compensator (DSSC) as a distributed power flow controller. It is low cost modules that can be attached directly on existing line using single turn transformer. MATLAB Simulation results shows significant power flow control through line using DSSC devices.

Detection and counting of blood cells using image segmentation: A review

Abstract: In medical field blood testing is considered to be one of the most important clinical examination test. In clinical laboratory counting of different types of blood cells is important for physician to diagnose the diseases in particular patient. Manual microscopic inspection of blood cells is time consuming and requires more technical knowledge. Therefore there is a need to research for an automated blood cell detection system that will help physician to diagnose diseases in fast and efficient way. Many researchers have done their research for counting blood cells using different methodologies. This paper reviews different methodologies that have been used for blood cell counting. The objective is to study these methodologies and identify future research direction in order to get more accuracy.

Solar PV emulator for realizing PV characteristics under rapidly varying environmental conditions

Abstract: Due to increasing importance of distributed generation and smart grid, solar PV systems are gaining more and more importance. However for the efficient design of the solar PV systems, solar emulator is necessary which mimics the actual PV characteristics. In this paper, a solar PV emulator with quasi sliding mode controller is presented which can simulate the real time PV characteristics under varying insolation and temperature. The advantage of the proposed emulator is that it can produce accurate I–V characteristics under fast varying environmental conditions. A low cost microcontroller based controller is developed for building the laboratory prototype of emulator. Moreover the software interfacing with user friendly GUI is developed. The proposed controller and emulator hardware can be useful for various applications like MPPT system design for automobile applications, battery chargers, inverters and grid connected systems.

Ant Colony Optimization applied to selective harmonic elimination in Multilevel inverters

Abstract: For medium and high voltage applications, Multilevel inverters have been widely used as a important devices. The advantages of multilevel inverters include low electromagnetic interference (EMI) outputs, low power dissipation, low harmonic etc. The most common multilevel inverter topology is cascaded H-bridge topology constituted by IGBT semiconductors. The most common switching technology used is SPWM to obtain staircase voltage waveform. This staircase waveform contains harmonics and fundamental component. The requirement of satisfying the fundamental component is that all harmonics should be removed. The higher order harmonics can be easily removed by using filters. But lower order harmonics cannot be easily eliminated. For removing lower order harmonics non-linear transcendental equations derived from fourier series expansion should be solved. Solution to these equations can be found out by using computing methods. This paper presents a different approach, which is a advanced computing method i.e. Ant Colony Optimization method. By using ACO elimination of lower order harmonics is possible. The results shows 3rd, 5th, 7th harmonics are eliminated whereas THD is also reduced. MATLAB/Simulink software is used to validate these results.

GA based hybrid selective harmonic elimination (SHE) technique applied to five-level Nested Neutral Point Clamped (NNPC) Converter

Abstract: This paper presents, genetic algorithm based hybrid selective harmonic elimination scheme for recently introduced Nested Neutral Point Clamped (NNPC) Converter. The Selective harmonic elimination (SHE) modulation scheme reduces device stress, switching losses and filter size in high power and high voltage applications. SHE technique aims to solve non-linear and transcendental equations while keeping the objective, to maintain the fundamental harmonic component at its reference value and to eliminate lower order odd harmonics. To solve these nonlinear equations Hybrid algorithm has been adopted in this paper. This algorithm has two stages, during first stage GA has been run for four iterations and in second stage obtained solution from GA is used to initialize newton algorithm, which finally gives the exact converged solution. Thus, proposed algorithm overcomes the drawback of newton algorithm to have strong initial guess. This work also investigates the performance of five-level NNPC inverter by doing spectral analysis of phase and line voltages. The MATLAB/SIMULINK software is used for comprehensive simulation of five-level NNPC inverter.

Genetic algorithm (GA) based SHE technique applied to seven-level Nested Neutral Point Clamped (NNPC) Converter

Abstract: This paper presents, selective harmonic elimination technique based on genetic algorithm applied to recently introduced seven-level Nested Neutral Point Clamped (NNPC) Converter. The Selective harmonic elimination (SHE) technique aims to eliminate lower order harmonic and maintain reference value of fundamental component. This demands the solution of nonlinear and transcendental equations. Thus, optimization problem has been formulated by defining proper objective function which covers all the constraints. GA is a matured and well known optimization algorithm, hence it is preferred to solve the concerned optimization problem. Solution gives the switching angles to switch the inverter. In this work, switching angles are determined offline for seven-level inverter, which are tuned for eliminating fifth and seventh harmonics. The MATLAB/SIMULINK software is used for comprehensive simulation of seven-level NNPC converter.

NEMA: Node Energy Monitoring Algorithm for Zone Head Selection in mobile ad-hoc network using residual battery power of node

Abstract: The Zone Routing Protocol (ZRP) is emerging as a potential hybrid routing algorithm. By using two kinds of routing protocol i.e. IARP and IERP, ZRP not only abates control overhead, but also minimizes end-to-end delay. The resent research on performance of ZRP indicates that routing overhead is still a significant issue and need more improvements. In this paper we focus on improving ZRP protocol by adding energy constraints in it so that the protocol works efficiently in MANET and improves network lifetime. To implement this we divide our proposed algorithm in two parts. In first part we design Zone Head Selection Algorithm (ZHSA) to make various zones and then select zone head (ZH) such that it must have maximum residual power. For this we use Max-heap tree concept to select maximum residual power node which act as ZH in our network. In second part, we design Node Energy Monitoring Algorithm (NEMA) which monitor change in the residual energy of each node and set different phases to each node based on residual energy levels. By using this mechanism the node who acts as ZH will not die because of energy starvation and hence the network lifetime is improved to some extent.

An asymmetrical multilevel inverter topology with reduced source count

Abstract: In this paper, an asymmetrical topology for cascaded multilevel inverter based on basic converter unit, series unit and full-bridge is proposed. It offers lower total harmonic distortion, switching losses and voltage stress on switches than conventional inverters. An algorithm to determine dc voltage sources magnitudes is proposed. The gating signals for the power switches are generated by employing Nearest Level Control (NLC) method. This structure allows a reduction of the system cost and size. Effectiveness of the proposed topology has been demonstrated by analysis and simulation.

Automated content based short text classification for filtering undesired posts on Facebook

Abstract: Online Social Networking (OSN) sites are always helpful for being socialized and to get exposed to a social environment. But, privacy and prevention of undesired posts on user wall is the only problem of biggest concern. User should have the ability to control the message posted on their own private wall to avoid undesirable contents to be displayed. The existing OSN sites have very little support regarding this problem. For example, Facebook filters messages on the basis of identity of sender i.e. only friend, friend of friend or group of friends can post any message; no content based preferences are supported. Taking this fact into consideration, the proposed work contributes to address such problem through a machine learning based soft classifier for labeling messages in support of contents of message. This work experimentally evaluates an automated scheme to filter out unwanted messages posted on Facebook walls by assigning a set of categories with each short text message based on its contents.

Design of low power Schmitt trigger logic gates using VTCMOS

Abstract: This paper presents Subthreshold Design of Schmitt trigger logic gates for low power operation by using Variable Threshold CMOS Technique (VTCMOS).The proposed design of Schmitt trigger are form on buffer design using dynamic threshold MOS (DTMOS) for better low power operation. By improving the Schmitt trigger to AND/OR/XOR Gates, with minimum switching power consumption as well as area reduction in comparison with CMOS Schmitt triggers, at the cost of a slight increase in delay. The performance characteristics of Schmitt trigger gates have been analyzed in term of power dissipation and delay using predictive Technology models at 180nm technology node for both CMOS and VTCMOS Schmitt trigger.

Analysis of various approaches used for the implementation of QCA based full adder circuit

Abstract: Quantum Dot Cellular automata, one of the emerging nanotechnology is the possible alternative to these problems. This paper presents the comparative analysis of various QCA methodologies used for the implementation of full adder circuit. Also the designs and performance analysis of QCA full adder using Majority gate, minority gate, multilayer wire crossing, 5 input Majority voter gate is discussed. The designs follow the conventional design approaches, but due to the technology differences, they are modified for the best performance in QCA. The layout and simulation results are presented using QCADesigner Tool. QCADesigner is a QCA layout and simulation tool developed at the University of Calgary [1]. Simulations indicate very attractive performance regarding complexity, area, and delay in Minority gate based full adder and 5 input MV gate based full adder.

Implementation of optimized vedic multiplier using CMOS technology

Abstract: This paper presents design of optimized high speed and low power Vedic multiplier based on Vedic sutra Urdhva Tiryagbhyam. Adiabatic logic is used to reduce the power consumption of Vedic multiplier and its performance is evaluated by comparing it with conventional MOS design. The power consumption of Adiabatic Vedic multiplier is less than power consumed by Vedic multiplier without adiabatic logic is analyzed. The circuit 2×2, 4×4 Vedic multipliers are designed and simulated on 180nm technology using Tanner EDA Tool 13.0.

Secured cloud architecture for cloud service provider

Abstract: Todays world is of cloud computing, cloud service provider (CSP) provides different resources and services to the user anytime anywhere over the internet. Due to this feature of cloud maintain security over cloud is complex. Cloud computing security issue are authentication of user, nonrepudiation, authority, confidentiality, privacy, availability, access control and checking the integrity of data. Here we have proposed the secure architecture for cloud which is going to map some cloud security issues that are authentication of user, confidentiality, privacy, access control and checking the integrity of data. For authentication of user system uses One Time Password (OTP), for data integrity check system uses modified SHA-2 hash function. This modified version of SHA-2 will provide better solution for PreImage attack and Collision attack and for encryption and decryption system uses standard Advanced Encryption Standards (AES) algorithm.

Dual band logo antenna for WLAN application

Abstract: In this paper, logo antenna for WLAN application is proposed. This logo-type antenna represents the logo of Nagpur Engg. autonomous college (Yeshwantrao chavan college, Nagpur-India). The dual band college logotype antenna of size 40mm × 50mm × 1.6mm is presented. In this paper the design of a dual band logo antenna consists of three letters, YCC. This antenna give the dual band, first band from 2.4214 GHz to 3.0742 GHz and second band from 4.7462 GHz to 6.2313 GHz. FR4 substrate with relative permittivity, e r = 4.3 is used for the proposed antenna design. In this paper the antenna performance in terms of resonance frequency, return loss, radiation pattern, antenna gain, directivity and bandwidth is observed.

A novel shape octagonal koch fractal MIMO antenna for WLAN and WiMAX application

Abstract: In this paper, a tri band compact octagonal fractal monopole MIMO antenna is presented. The proposed antenna is microstrip line fed and its structure is based on fractal geometry where the resonance frequency of antenna is lowered by applying iteration techniques. The simulated bandwidth of the antenna are 2.3706GHz to 2.45GHz, 3.398GHz to 3.677GHz and 4.9352GHz to 5.8988GHz (S11 < −10 dB), covering the bands of WLAN and WiMAX. The characteristics of small size, nearly omnidirectional radiation pattern and moderate gain make the proposed MIMO antenna entirely applicable to WLAN and WiMAX applications. The proposed antenna has compact size of 50 mm × 50 mm. Details of the proposed antenna design and performance are presented and discussed.

Quadtree partitioning and extended weighted finite automata-based fractal colour video coding

Abstract: Fractal coding technique has become the most popular coding technique in the recent development of image/video compression technologies for its better performance, achieving a high compression ratio, less decoding time and good reconstruction quality of image. This paper elaborates on the approach which is a combination of a quadtree partitioning scheme and extended weighted finite automata (EWFA) coding for fractal video compression based on the concept of intra-frame coding. The quadtree partitioning scheme is used to specify the address of each sub-image. It is observed that any image can be represented by the quadtree-based EWFA; the quadtree-based EWFA coding process is similar to fractal coding process; and also the size of domain pool increases dynamically during the process of quadtree-based EWFA encoding as that of in fractal coding. Experimentations are carried on standard databases like Soccer, Suzie, Bus, Football, Xylophone, Paris, Traffic, Akiyo, Ice and mobile sequence. The developed basic fractal image compression existing mechanism is also further implemented on video/image sequences based on the concept of intra-frame coding used for comparing the results with the proposed approach. Experimental results show that the EWFA encoding/decoding process improves the quality, compression ratio, encoding and decoding time of reconstructed image sequence.

VLSI design of analog multiplier in weak inversion region

Abstract: In Analog application, multipliers plays a vital role. They are used in many fields like artificial neural networks, image processing, modulators etc. In this paper, a low power and low voltage CMOS analog multiplier is presented with performance analysis and design implementation by using Exponential Approximation circuit. In this design, MOSFETS are operating in weak inversion region in order to achieve low power dissipation. Multiplier consists of four such Exponential approximation circuits which is operating at a supply of 0.5V. Results and simulations are carried out by using 180nm technology in Tanner tool. Total power consumption is 598nW. T-Spice simulation and result shows that the proposed structure has very low power consumption which makes it attractive for using in various analog circuits.