Proceedings ArticleDOI
A 10 Gbps eye opening monitor in 65nm CMOS
Sandeep Krishnan,Shanthi Pavan +1 more
- pp 3028-3031
TLDR
This work describes the working principle and design details of a low cost, on-chip monitor circuit that enables the determination of the eye diagram and demonstrates the efficacy of the techniques.Abstract:
Monitoring the eye diagram at the output of an embedded analog adaptive equalizer used in a high speed serial link is challenging. Eye measurement using an external oscilloscope is problematic due to the bandwidth of the test setup. In this work, we describe the working principle and design details of a low cost, on-chip monitor circuit that enables the determination of the eye diagram. The eye opening monitor (EOM), implemented in a 65 nm CMOS process, occupies 0.06 mm2 and consumes 5.7 mW from a 1.2 V supply. Measurements demonstrate the efficacy of our techniques.read more
Citations
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Journal ArticleDOI
A 10-Gb/s Eye-Opening Monitor Circuit for Receiver Equalizer Adaptations in 65-nm CMOS
Yu-Chuan Lin,Hen-Wai Tsao +1 more
TL;DR: Results show that the reported horizontal eye-opening value is proportional to the value from a real eye diagram monitor from the test buffer, and a novel multi-phase generator circuit with a delay gain calibration is demonstrated.
References
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Journal ArticleDOI
500-MS/s 5-bit ADC in 65-nm CMOS With Split Capacitor Array DAC
TL;DR: In this article, a 500-MS/s 5-bit ADC for UWB applications has been fabricated in a 65-nm CMOS technology using no analog-specific processing options.
Proceedings Article
500-MS/s 5-bit ADC in 65-nm COMS with split capacitor array DAC
TL;DR: In this paper, a 500-MS/s 5-bit ADC for UWB applications has been fabricated in a 65-nm CMOS technology using no analog-specific processing options, and the ADC achieves Nyquist performance with an SNDR of 27.8 and 26.1 dB for 3.3 and 239 MHz inputs, respectively.
Proceedings ArticleDOI
Fast eye monitor for 10 Gbit/s and its application for optical PMD compensation
TL;DR: The excellent correlation between high speed eye monitor signal and BER shows the potential for fast tracking of eye fluctuations and performance monitoring.
Journal ArticleDOI
A 10-Gb/s two-dimensional eye-opening monitor in 0.13-/spl mu/m standard CMOS
TL;DR: In this article, an eye-opening monitor (EOM) architecture that can capture a two-dimensional (2D) map of the eye diagram of a high-speed data signal has been developed, which uses two single-quadrant phase rotators and one digital-to-analog converter (DAC) to generate rectangular masks with variable sizes and aspect ratios.
Journal ArticleDOI
A 10 Gb/s eye opening monitor IC for decision-guided optimization of the frequency response of an optical receiver
TL;DR: In this paper, a single chip eye opening monitor (EOM) is used as part of a signal processing unit for TDM transmissions on long haul fiber links, which is not only limited by the speed of electronic components but also by problems like fiber dispersion, polarization mode dispersion and fiber nonlinearities.