A Comparative Study of High Speed CMOS Adders using Microwind and FPGA
TLDR
Simulation results show that a 4-bit carry select adder provides a better performance at the cost of power dissipation as 89.211 μW compared with 38.414 μW by a ripple carry adder with 0.12 μm technology processes.Abstract:
In the current semiconductor technology evolution, there is a huge demand in designing a low power, high speed adders with less area. As adders are essential components in the data-path of any computer system, adder modules are needed to be enhanced for better performance. One such efficient adder implementation is the Carry Look-Ahead Adder (CLA) which is designed to overcome the latency introduced by rippling effect of carry bits in a conventional Ripple Carry Adder (RCA). Further, the use of this CLA module in the place of Ripple Carry Adder module inside a Carry Select Adder (CSEA) is proposed for increased speed. Also, a novel implementation of adder, making use of the fact that the sum and carry are compliment of one another, except when all the inputs are same is presented. Simulation results show that a 4-bit carry select adder provides a better performance at the cost of power dissipation as 89.211 μW compared with 38.414 μW by a ripple carry adder with 0.12 μm technology processes. In this study, these high speed adders are implemented with the help of the Digital Schematic (DSCH) software tool, Micro wind layout editor tool and Quartus II synthesis software tool. This Quartus II synthesis tool is used for the implementation of adders on Altera EP2C20F484C7 FPGA device. These kinds of adders are further to be extended to build high-speed multipliers which are most important for the applications like digital signal processors, microprocessors, etc.read more
Citations
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Journal ArticleDOI
Study and Analysis of CMOS Carry Look Ahead Adder with Leakage Power Reduction Approaches
TL;DR: From this paper work that only an applicable selection of leakage power reduction approach for a particular function will be well borne by a Very Large Scale Integrated (VLSI) circuit design depend on progressive analytical method.
Journal ArticleDOI
Low - Power and Area - Efficient Square - Root Carry Select Adders using Modified XOR Gate
G. Ragunath,R. Sakthivel +1 more
TL;DR: A 2-input XOR gate is accomplished by a modified design which gives better result when the adder circuit has more number of XOR gates, so the results show that Area – Delay – Product (ADP) has been reduced in proposed circuits.
References
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Book
Practical Low Power Digital VLSI Design
TL;DR: This tutorial was developed when I developed a company wide training class Tutorial on Low Power Digital VLSI Design for designers in Motorola The feedback from the tutorial attendees helps to improve the quality of the training.
Book
Fundamentals of Digital Logic with VHDL Design
TL;DR: Basic concepts in digital logic design are introduced using simple logic circuits, which are designed by using both manual techniques and modern CAD-tool-based methods.
Book
Introduction to VLSI Circuits and Systems
TL;DR: The CD has two versions of the SPICE simulator (AIM-SPICE and MicroCap6), and a Verilog simulation environment (Silos III) and a short presentation entitled "Stick Diagrams" in .pdf format that supplements the text discussion.
Book
Low Voltage, Low Power VLSI Subsystems
Kiat Seng Yeo,Kaushik Roy +1 more
TL;DR: This monograph details cutting-edge design techniques for the low power circuitry required by the many new miniaturized business and consumer products driving the electronics market.
Journal ArticleDOI
An area-efficient static CMOS carry-select adder based on a compact carry look-ahead unit
G. A. Ruiz,Mercedes Granda +1 more
TL;DR: This paper presents a highly area-efficient CMOS carry-select adder (CSA) with a regular and iterative-shared transistor structure very suitable for implementation in VLSI.
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