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Proceedings ArticleDOI

Multi precision arithmetic adders

TLDR
A novel technique for designing a new Carry Select adder for multi precision arithmetic circuits like low latency and less power consumption and along with less gate count is introduced.
Abstract
Arithmetic adder is the most important basic element for many digital applications. In this paper different types of adders are taken for experimental study such as Ripple Carry Adder, Carry Save adder, Carry Look ahead adder, Carry Increment adder, Carry Select adder, and Carry Skip adder. Here in this paper introducing a novel technique for designing a new Carry Select adder for multi precision arithmetic circuits. By using this technique improvements has been achieved like low latency and less power consumption and along with less gate count. Experimentally synthesized and simulated by using Xilinx ISE14.7, also tested in SPARTAN3E, XC3S1600E with speed of −5.

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Citations
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Proceedings ArticleDOI

Design and implementation of 32-bit adders using various full adders

TL;DR: The design and the implementation of various 32-bit adders like Ripple Carry Adder, Carry Increment adder and Carry bypass adder for different full adder cells is done using the Verilog HDL.
Journal ArticleDOI

A new scalable parallel adder based on spiking neural P systems, dendritic behavior, rules on the synapses and astrocyte-like control to compute multiple signed numbers

TL;DR: The results show that the implementation on a low-area low-cost FPGA requires small amount of circuitry, which potentially allows the development of highly parallel architectures that can be used in advanced applications, such as portable mobile robots, mobile devices, image and vision processing, among others.
References
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Journal ArticleDOI

A Regular Layout for Parallel Adders

TL;DR: It is shown that addition of n-bit binary numbers can be performed on a chip with a regular layout in time proportional to log n and with area proportional to n.
Journal ArticleDOI

Low-Power and Area-Efficient Carry Select Adder

TL;DR: This work uses a simple and efficient gate-level modification to significantly reduce the area and power of the CSLA, and develops and compared with the regular SQRT C SLA architecture.
Journal ArticleDOI

Ultra low-voltage low-power CMOS 4-2 and 5-2 compressors for fast arithmetic circuits

TL;DR: Simulation results show that the 4- 2 compressor with the proposed XOR-XNOR module and the new fast 5-2 compressor architecture are able to function at supply voltage as low as 0.6 V, and outperform many other architectures including the classical CMOS logic compressors and variants of compressors constructed with various combinations of recently reported superior low-power logic cells.
Journal ArticleDOI

A reduced-area scheme for carry-select adders

TL;DR: The author introduces a scheme to generate carry bits with block-carry-in 1 from the carries of a block withBlock- Carry-in 0 to derive a more area-efficient implementation for both the carry-select and parallel-prefix adders.
Journal ArticleDOI

High-speed binary adder

TL;DR: A new scheme is presented in which the new carry propagation is examined by including the neighboring pairs (ai, bi; ai+1, bi+1), which not only reduces the component count in design, but also requires fewer logic levels in adder implementation.
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