Proceedings ArticleDOI
A high performance 2-dimensional VLSI architecture for H.264/AVC Variable Block Size integer motion estimation
N. Aarthi,K. S. Athishkarthic,N. Madhan Kumar,P. Jayakrishnan +3 more
- pp 1-4
TLDR
This paper proposes parallel 2-D architecture for computing the Motion Vectors (MV) using 16 Processing Element with Carry Save Adder (CSA) compressor and comparators to compute Sum of Absolute Differences (SAD) of 4×4 macro block.Abstract:
Variable Block Size (VBS) motion estimation has been adopted by H.264/AVC for its compression efficiency and high video quality. In this paper we propose parallel 2-D architecture for computing the Motion Vectors (MV). This 2-D systolic array architecture is composed of 16 Processing Element (PE) with Carry Save Adder (CSA) compressor and comparators to compute Sum of Absolute Differences (SAD) of 4×4 macro block. By data reuse scheme using raster scan method the Sum of Absolute Difference (SAD) for variable blocks 8×4, 4×8, 8×8, 16×8, 8×16, 16×16 are computed from the SAD of 4×4 sub blocks resulting in 41 SADs. With the reduced computational complexity for the search range [16×16] our design operates at the frequency of 689.65MHz with the throughput of 43.1Mega blocks per second and the power dissipation is 246.13μW. Our design is synthesized by using Cadence RTL Compiler using TSMC 45nm CMOS technology with a gate count of 21.742k gates.read more
Citations
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Journal ArticleDOI
A Complete Verification of a Full Search Motion Estimation Engine
TL;DR: The proposed Motion Estimation architecture smartly reuses the data fetched from the main memory to be used in the search area to allow using less memory I/O bandwidth and high video quality.
References
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Journal ArticleDOI
Video coding with H.264/AVC: tools, performance, and complexity
Jörn Ostermann,J. Bormans,P. List,Detlev Marpe,Matthias Narroschke,Fernando Pereira,Thomas Stockhammer,Thomas Wedi +7 more
TL;DR: This paper provides an overview of the new tools, features and complexity of H.264/AVC.
Book
The H.264 Advanced Video Compression Standard
TL;DR: This book unravels the mysteries behind the latest H.264 standard and delves deeper into each of the operations in the codec, providing readers with practical advice on how to get the most out of the standard.
Journal ArticleDOI
A family of VLSI designs for the motion compensation block-matching algorithm
K.-M. Yang,Ming-Ting Sun,L. Wu +2 more
TL;DR: In this article, a family of modular VLSI architectures and chip implementations of the motion-compensation full-search block-matching algorithm are described, motivated by the intensive computations required to perform motion compensation in real time.
BookDOI
The H.264 Advanced Video Compression Standard: Richardson/The H.264 Advanced Video Compression Standard
Journal ArticleDOI
A VLSI architecture for variable block size video motion estimation
Swee Yeow Yap,John V. McCanny +1 more
TL;DR: A new one-dimensional (1-D) very large-scale integration architecture for full-search VBSME (FSVBSME), which can process up to 41 MV sub-blocks (within a macroblock) in the same number of clock cycles.