Proceedings ArticleDOI
A high-speed and low-latency Reed-Solomon decoder based on a dual-line structure
Hyeong-Ju Kang,In-Cheol Park +1 more
- Vol. 3, pp 3180-3183
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TLDR
In this article, the authors proposed a new decoding structure of Reed-Solomon codes that can operate as fast as the serial structure and has as short latency as the parallel structure.Abstract:
This paper presents a new decoding structure of Reed-Solomon ( RS) codes that are widely used for channel coding. Although many decoding structures have been developed, the serial structures have long latency and the parallel structures are not fast enough to deal with the demands of high-speed decoding. To achieve both short latency and fast ope,ration, the summation of the products of syndromes is eliminated and the difference used to calculate the error locator polynomial is incrementally updated. The proposed structure called a dual-line structure can operate as fast as the serial structure and has as short latency as the parallel structure. In addition, the dual-line structure is regular and easy to implement. Experimental results confirm these advantages at the cost of a small hardware increase.read more
Citations
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Proceedings ArticleDOI
High-Throughput and Low-Power Architectures for Reed Solomon Decoder
Akash Kumar,Sergei Sawitzki +1 more
TL;DR: A uniform comparison between various algorithms and architectures used for Reed Solomon (RS) decoder, and the results obtained are very encouraging both in terms of silicon area and power.
Journal ArticleDOI
Multistandard FEC Decoders for Wireless Devices
TL;DR: This overview paper reviews the possibilities for combinations of common decoder families (Reed-Solomon, Viterbi, Turbo and low-density parity check) within one hardware platform and shows, that although specific combinations may result in silicon area savings, in general case the reuse possibilities are limited to much less of the overall decoder area.
Book
Intelligent Algorithms in Ambient and Biomedical Computing
TL;DR: This book is the outcome of a series of discussions at the Philips Symposium on Intelligent Algorithms, held in Eindhoven in December 2004 and contains topics such as bioscience computing, database design, machine consciousness, scheduling, video summarization, audio classification, semantic reasoning, machine learning, tracking and localization, secure computing, and communication.
Proceedings ArticleDOI
Hardware implementation of shortened (48,38) Reed Solomon forward error correcting code
M.A. Khan,S. Afzal,R. Manzoor +2 more
TL;DR: A shortened (48,38) Reed Solomon (RS) forward error-correcting code from a hardware implementation point of view is presented.
Patent
Error-locator-polynomial generation with erasure support
TL;DR: In this article, the erasure identification information is used to more easily decipher the overall codeword when faced with a error-filled codeeword, and a method for correcting errors in an ECC block using erasure-identification data when generating an error-locator polynomial.
References
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Book
Algebraic Coding Theory
TL;DR: This is the revised edition of Berlekamp's famous book, "Algebraic Coding Theory," originally published in 1968, wherein he introduced several algorithms which have subsequently dominated engineering practice in this field.
BookDOI
Reed-Solomon Codes and Their Applications
TL;DR: R Reed-Solomon Codes and the Design of Sequences for Spread-Spectrum Multiple-Access Communications, edited by D. McEliece and L. Pursley.
Journal ArticleDOI
VLSI design of inverse-free Berlekamp-Massey algorithm
TL;DR: The Berlekamp-Massey iterative algorithm for decoding BCH codes is modified to eliminate the calculation of inverses, which is useful in the practical application of multiple-error-correcting BCH or RS codes.
Journal ArticleDOI
Inversionless decoding of binary BCH codes
TL;DR: The iterative algorithm for decoding binary BCH codes presented by Berlekamp and, in an alternative form, by Massey is modified to eliminate inversion.
Journal ArticleDOI
A Reed-Solomon product-code (RS-PC) decoder chip for DVD applications
TL;DR: The authors present an RS-PC decoder chip with a dual-frame-buffer architecture that can be eliminated with embedded frame buffers and limited in speed by the off-chip frame buffer to about 18 MHz.