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A Linear-Centric Modeling Approach to Harmonic Balance Analysis

TLDR
The efficacy of this linear-centric methodology further improves with increasing model complexity, the inclusion of interconnect parasitics and other analyses that are otherwise difficult with traditional nonlinear models.
Abstract
In this paper, we propose a new harmonic balance simulation methodology based on a linear-centric modeling approach. A linear circuit representation of the nonlinear devices and associated parasitics is used along with corresponding time and frequency domain inputs to solve for the nonlinear steady-state response via successive chord (SC) iterations. For our circuit examples, this approach is shown to be up to 60/spl times/ more run-time efficient than traditional Newton-Raphson (N-R) based iterative methods, while providing the same level of accuracy. This SC-based approach converges as reliably as the N-R approaches, including for circuit problems which cause alternative relaxation-based harmonic balance approaches to fail. The efficacy of this linear-centric methodology further improves with increasing model complexity, the inclusion of interconnect parasitics and other analyses that are otherwise difficult with traditional nonlinear models.

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Citations
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Patent

Dynamic array architecture

TL;DR: In this paper, a linear gate electrode track that extends over both a diffusion region and a non-active region of the substrate is defined to minimize a separation distance between ends of adjacent linear gate electrodes segments within the linear-gated electrode track, while ensuring adequate electrical isolation between the adjacent linear gated electrode segments.
Patent

Methods for Defining Dynamic Array Section with Manufacturing Assurance Halo and Apparatus Implementing the Same

TL;DR: In this paper, a method for defining a dynamic array section to be manufactured on a semiconductor chip is described, which includes defining a peripheral boundary of the dynamic array and a manufacturing assurance halo outside the boundary.
Proceedings ArticleDOI

Nonlinear distortion analysis via linear-centric models

TL;DR: An efficient distortion analysis methodology is presented for analog and RF circuits that utilizes linear-centric circuit models to generate individual distortion contributions due to the various circuit nonlinearities, which provides important design insights regarding the relationships between design parameters and circuit linearity, hence the overall system performance.
Patent

Methods for defining contact grid in dynamic array architecture

TL;DR: In this article, the vertical connection structures are placed at a number of gridpoints within a vertical connection placement grid so as to provide electrical connectivity between layout features in the lower and higher chip levels.
Patent

Cell circuit and layout with linear finfet structures

TL;DR: In this paper, a cell circuit and corresponding layout is disclosed to include linear-shaped diffusion fins defined to extend over a substrate in a first direction so as to extend parallel to each other.
References
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Book

Iterative Solution of Nonlinear Equations in Several Variables

TL;DR: In this article, the authors present a list of basic reference books for convergence of Minimization Methods in linear algebra and linear algebra with a focus on convergence under partial ordering.
Journal ArticleDOI

PRIMA: passive reduced-order interconnect macromodeling algorithm

TL;DR: In this article, an algorithm for generating provably passive reduced-order N-port models for linear RLC interconnect circuits is described, in which, in addition to macromodel stability, passivity is needed to guarantee the overall circuit stability.
Book

Steady-state methods for simulating analog and microwave circuits

TL;DR: This chapter discusses the design and implementation of the APFT Time-Point Selection Algorithm, and some of the methods used to construct the Transform Matrix, which simplifies the selection process.
Journal ArticleDOI

A charge-oriented model for MOS transistor capacitances

TL;DR: A new model for computer simulation of capacitance effects in MOS transistors is presented, which guarantees conservation of charge and includes bulk capacitances.
Book

Fundamentals of Computer-Aided Circuit Simulation

TL;DR: In this paper, the authors present a series of integration formulas for circuit equations, including the following: 1.1 Branch Constitutive Equations, 2.2 Nodal Analysis, 3.4 Sparse Tableau Analysis, 4.1 Newton-Raphson Iteration, 5.4 Internal Device Node Suppression and 5.5 Stability of Integration Methods, 6.1 Adjoint Networks and Sensitivity.