Patent
A self-routing switching network.
Alan Huang,Scott C Knauer +1 more
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TLDR
In this article, a self-routing switching network consisting of a conventional self routing sorting network (20) followed by a self routing expander (40) is described. But the authors do not specify the destination address of the input signal.Abstract:
A full access, non-blocking, wide band switching network that is self routing. Responsive to input signals having embedded destination addresses, the self routing switching network comprises a conventional self routing sorting network (20) followed by a self routing expander (40). Incoming signals are ordered, and simultaneously appear at the output of the sorting network (20) in ascending order of destination addresses. The signals incoming to the expander network (40) are also processed simultaneously. The processing consists of relating the intermediate address of the expander network input line (1300) at which each signal appears with the destination address of the signal, and steering the signal to the appropriate output line (1400).read more
Citations
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Journal ArticleDOI
Nonblocking copy networks for multicast packet switching
TL;DR: A nonblocking, self-routing copy network with constant latency is proposed, capable of packet replications and switching, which is usually a serial combinations of a copy network and a point-to-point switch.
Patent
Inter-computer message routing system with each computer having separate routinng automata for each dimension of the network
TL;DR: In this article, the authors present a method and apparatus for routing message packets between the nodes in a multicomputer, which comprises providing a routing circuit at each node and interconnecting the routing circuits to define communications paths, along which message packets can be routed; at each routing circuit, forming routes to other nodes as a sequence of direction changing and relative address indicators for each node between the starting node and each destination node; receiving a message packet to be transmitted to another node and an associated destination node designator therefor; retrieving the route to the destination node from a memory
Patent
Interprocessor switching network
Read Edgar Lawrence,Grant Elwyn Everett,Keto Gary Alan,Sharlene Chieh-Hsia Lin,Morgan James Douglas,Robert E. Nimon,Oliver Gene Oldham,Allen Ray Adams,Salmones Jose Aurelio +8 more
TL;DR: In this paper, a digital switching network for providing simultaneous connections among user processors of processor-based communications equipment is presented, where the user processors act as originators and destinations of data communications packets.
PatentDOI
Buffer management system
TL;DR: In this paper, a buffer management system for a general multipoint packet switching network is proposed, which determines whether a packet should be stored, retransmitted, or discarded during an overload condition by identifying each incoming packet as either an excess packet or a nonexcess packet based on the number of packets stored in the memory array.
Journal ArticleDOI
Performance comparison between optoelectronic and VLSI multistage interconnection networks
TL;DR: Based on the assumed technology parameters, optoelectronics outperforms VLSI in bandwidth for network sizes above 256 and higher speed and lower area for large networks.
References
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Proceedings ArticleDOI
Sorting networks and their applications
TL;DR: To achieve high throughput rates today's computers perform several operations simultaneously; not only are I/O operations performed concurrently with computing, but also, in multiprocessors, several computing operations are done concurrently.
Journal ArticleDOI
Access and Alignment of Data in an Array Processor
TL;DR: This paper discusses the design of a primary memory system for an array processor which allows parallel, conflict-free access to various slices of data, and subsequent alignment of these data for processing, and a network based on Stone's shuffle-exchange operation is presented.
Journal ArticleDOI
A Self-Routing Benes Network and Parallel Permutation Algorithms
TL;DR: A Benes permutation network capable of setting its own switches dynamically and leading to efficient O(log N) parallel algorithms to perform the same class of permutations on cube connected and perfect shuffle computers.
Patent
Switching circuit for digital packet switching network
TL;DR: In this article, a switching circuit comprises an interface to the interior which comprises two-way gates which are connected to internal interfaces of other switching circuits of the network, each of said gates comprising a l-input and n-output receive circuit and an n-input-and l-output transmit circuit, one input of the transmit circuit being connected to the output of a receive circuit different for each of the n inputs, and the input of each receive circuit of a gate of a gating node connecting to the outputs of another gate of another switching circuit of said network.