A study of the single event effects impact on functional mapping within flash-based FPGAs
Francesco Abate,Luca Sterpone,Massimo Violante,F. Lima Kastensmidt +3 more
- pp 1226-1229
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TLDR
A new methodology to identify the most critical switches inside the configuration logic block and the most redundant and robust configuration selection for each logic function is proposed and it is shown that by using the most robust functional mapping it is possible to enhance the reliability of the entire design with respect to a not robust ones.Abstract:
Flash-based FPGAs are increasingly demanded in safety critical fields, in particular space and avionic ones, due to their non-volatile configuration memory. Although they are almost immune to permanent loss of the configuration data, they are composed of floating gate based switches that can suffer transient effects if hit by high energetic particles with critical consequences on the implemented logic. This paper presents a new way for the analysis of the impact of Single Event Effects in Flash-based FPGAs. We proposed a new methodology to identify the most critical switches inside the configuration logic block and the most redundant and robust configuration selection for each logic function. The experimental results achieved by fault injection demonstrated the feasibility of the proposed method and show that by using the most robust functional mapping it is possible to enhance the reliability of the entire design with respect to a not robust ones.read more
Citations
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References
More filters
Journal ArticleDOI
Collection of Charge on Junction Nodes from Ion Tracks
TL;DR: In this paper, an approximate analytical solution expressed as I(t) = Io [exp(-?t) - exp (-st)] (1) where Io is approximately the maximum current, 1/? is the collection time constant of the junction, and 1/s is the time constant for initially establishing the ion track.
Proceedings ArticleDOI
On the Optimal Design of Triple Modular Redundancy Logic for SRAM-based FPGAs
TL;DR: The experimental results presented in this paper demonstrate that the number and placement of voters in the TMR design can directly affect the fault tolerance, ranging from 4.03% to 0.98% the number of upsets in the routing able to cause an error in theTMR circuit.
Journal ArticleDOI
A new reliability-oriented place and route algorithm for SRAM-based FPGAs
Luca Sterpone,Massimo Violante +1 more
TL;DR: A reliability-oriented place and route algorithm is presented that is able to effectively mitigate the effects of the considered faults and is demonstrated by extensive fault injection experiments showing that the capability of tolerating SEU effects in the FPGA's configuration memory increases up to 85 times with respect to a standard TMR design technique.
Journal ArticleDOI
Total ionizing dose effects on flash-based field programmable gate array
Jih-Jong Wang,S. Samiee,H.-S. Chen,C.-K. Huang,M. Cheung,J. Borillo,S.-N. Sun,B. Cronquist,John L. McCollum +8 more
TL;DR: In this article, the total ionizing dose effect on a commercial Flash-based field programmable gate array is investigated by gamma ray radiation, and the floating-gate threshold and logic propagation delay are measured with respect to the total dose.
Proceedings ArticleDOI
Fault tolerance implementation within SRAM based FPGA designs based upon the increased level of single event upset susceptibility
TL;DR: This paper addresses design mitigation schemes targeted for SRAM based FPGA CMOS devices with various degrees of fault tolerance demonstrated along with an analysis of its effectiveness.