A survey of CORDIC algorithms for FPGA based computers
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Citations
FPGA Design Methodology for Industrial Control Systems—A Review
Phase Coherence Imaging
A Parallel Hardware Architecture for Scale and Rotation Invariant Feature Detection
Reconfigurable Computing: Accelerating Computation with Field-Programmable Gate Arrays
Reconfigurable Computing Architectures
References
The CORDIC Trigonometric Computing Technique
A unified algorithm for elementary functions
Fourier Transform Computers Using CORDIC Iterations
Highly concurrent computing structures for matrix arithmetic and signal processing
Efficient Shift Registers, LFSR Counters, and Long Pseudo- Random Sequence Generators
Related Papers (5)
Frequently Asked Questions (15)
Q2. How can the arcsine function be computed?
The Arcsine can be computed by starting with a unit vector on the positive x axis, then rotating it so that its y component is equal to the input argument.
Q3. What is the rotation mode of the CORDIC rotator?
The rotation mode CORDIC rotator is also useful for performing general vector rotations, as are often encountered in motion correction and control systems.
Q4. What is the purpose of the shift registers?
The shift registers are necessary to extract the sign of the y or z element before the first bits (lsbs) reach the next addersubtractors.
Q5. Why is the performance of the adder subtractor decreasing?
the performance diminishes as the word width is increased because of the carry propagation times across the adders.
Q6. How many CLBs are used in the CORDIC processor?
The 16 bit, 8 iteration CORDIC processor shown in Figure 3 uses only 21 CLBs, and will run at bit rates up to about 90 MHz (mainly limited by the RAM write cycle).
Q7. What is the simplest way to compute the arctangent base representation of the angle?
For fixed angle rotations, as are encountered in such places as fast Fourier Transforms (FFTs), the arctangent base representation of the angle can be pre-computed and applied directly to the CORDIC rotator.
Q8. What is the logic used to extend the sign of the shifted cross term?
The adder subtractor in this case includes logic to extend the sign of the shifted cross term and to reset the adder subtractor between words.
Q9. How long does the bit parallel iterative solution take to process?
This translates to about a 1.5µS processing time, which is only about three and a half times longer than the best one could expect from the much larger bit parallel iterative solution.
Q10. What is the inverse of the rotator?
Unlessthe inverse is calculable by changing the mode of the rotator, its computation normally involves comparing the output to a target value.
Q11. How can the authors obtain an iterative CORDIC architecture?
An iterative CORDIC architecture can be obtained simply by duplicating each of the three difference equations in hardware as shown in Figure 1.
Q12. What is the polar to cartesian coordinates used in a radar target generator?
That design, used for polar to Cartesian coordinate transformations in a radar target generator, runs at 52 MHz (clock rate and data rate) in an XC4013E-2.
Q13. What is the nth iteration of the serial adders?
During the nth iteration, the results can be read from the outputs of the serial adders while the next initialization data is shifted into the registers.
Q14. What is the result of the shift register and multiplexer?
The result is the shift register and multiplexer for word lengths up to 16 bits are implemented in a single CLB (plus 8 CLBs for the 2 address sequencers and iteration counter, which are shared by the three shifters).
Q15. what is the ei angle in the hyperbolic coordinate system?
CORDIC iteration equations are then:x x m y dy y x dz z d ei i i i ii i i i ii i i i+ − + −+= − ⋅ ⋅ ⋅= + ⋅ ⋅ = − ⋅11122where ei is the elementary angle of rotation for iteration i in the selected coordinate system.