Analysis and Detection Of Errors In Implementation Of SHA-512 Algorithms On FPGAs

TLDR: This paper presents a detailed analysis of the propagation of errors to the output in the hardware implementation of SHA-512, and proposes an error detection scheme based on parity codes and hardware redundancy.

Abstract: The Secure Hash Algorithm SHA-512 is a dedicated cryptographic hash function widely considered for use in data integrity assurance and data origin authentication security services. Reconfigurable hardware devices such as Field Programmable Gate Arrays (FPGAs) offer a flexible and easily upgradeable platform for implementation of cryptographic hash functions. Owing to the iterative structure of SHA-512, even a single transient error at any stage of the hash value computation will result in large number of errors in the final hash value. Hence, detection of errors becomes a key design issue. In this paper, we present a detailed analysis of the propagation of errors to the output in the hardware implementation of SHA-512. Included in this analysis are single, transient as well as permanent faults that may appear at any stage of the hash value computation. We then propose an error detection scheme based on parity codes and hardware redundancy. We report the performance metrics such as area, memory, and throughput for the implementation of SHA-512 with error detection capability on an FPGA of ALTERA. We achieved 100% fault coverage in the case of single faults with an area overhead of 21% and with a reduced throughput of 11.6% with the error detection circuit.