Patent
Apparatus for spatial and temporal sampling in a computer memory system
TLDR
In this paper, an apparatus for sampling states of a computer system having a hierarchical memory arranged at a plurality of levels, the hierarchical memory storing data at addresses, is presented, which includes a selector for selecting memory transactions based on first state and transaction information.Abstract:
An apparatus for sampling states of a computer system having a hierarchical memory arranged at a plurality of levels, the hierarchical memory storing data at addresses. The apparatus includes a selector for selecting memory transactions based on first state and transaction information. The memory transactions are to be processed by the hierarchical memory. A trigger activates the selector based on second state and transaction information. A sampler stores states of the computer system that are identified with the selected instructions while processing the selected memory transactions in the hierarchical memory.read more
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References
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Proceedings ArticleDOI
Interrupt-based hardware support for profiling memory system performance
A. Goldberg,J. Trotter +1 more
TL;DR: This paper describes how to combine simple hardware support and sampling techniques to obtain empirical data on memory system behavior without appreciably perturbing system performance.
Patent
Instruction sampling instrumentation
TL;DR: In this article, a system and method for instrumenting the execution of instructions in an out-of-sequence execution machine is presented. But it does not address the problem of cache misses or other system conditions.
Patent
Active cache for a microprocessor
TL;DR: In this paper, an active cache memory for use with microprocessors is disclosed, which is capable of performing transfers from external random access memory independently of the encache misaligned references and to transfer data to the microprocessor in bursts.
Patent
Digital computer system with cache controller coordinating both vector and scalar operations
TL;DR: In this article, a vector logic is used to keep track of the vector length and block extra memory addresses generated by the execution unit for the vector elements, and also blocks the memory addresses of masked vector elements so that these addresses are not translated by the memory management unit.
Patent
Translation of multiple virtual pages upon a TLB miss
TL;DR: In this article, the address of each virtual page in a pre-defined block of, e.g. four, contiguous virtual pages, is separately translated through segment and/or page table lookup operations to yield corresponding page frame addresses.