Journal ArticleDOI
Architecture of the Pentium microprocessor
D. Alpert,D. Avnon +1 more
TLDR
The techniques of pipelining, superscalar execution, and branch prediction used in the Pentium CPU, which integrates 3.1 million transistors in 0.8-mu m BiCMOS technology, are described in this article.Abstract:
The techniques of pipelining, superscalar execution, and branch prediction used in the Pentium CPU, which integrates 3.1 million transistors in 0.8- mu m BiCMOS technology, are described. The technology improvements associated with the three most recent microprocessor generations are outlined. The Pentium's compatibility, performance, organization, and development process are also described. The compiler technology developed with the Pentium microprocessor, which includes machine-independent optimizations common to current high-performance compilers, such as inlining, unrolling, and other loop transformations, is reviewed. >read more
Citations
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Journal ArticleDOI
Compiler transformations for high-performance computing
TL;DR: This survey is a comprehensive overview of the important high-level program restructuring techniques for imperative languages, such as C and Fortran, and describes the purpose of each transformation, how to determine if it is legal, and an example of its application.
Journal ArticleDOI
Larrabee: a many-core x86 architecture for visual computing
Larry D. Seiler,Doug Carmean,Eric Sprangle,Tom Forsyth,Michael Abrash,Pradeep Dubey,Stephen Junkins,Adam T. Lake,Jeremy Sugerman,Robert Dale Cavin,Roger Espasa,Ed Grochowski,Toni Juan,Pat Hanrahan +13 more
TL;DR: This article consists of a collection of slides from the author's conference presentation, some of the topics discussed include: architecture convergence; Larrabee architecture; and graphics pipeline.
Proceedings ArticleDOI
Optimization of instruction fetch mechanisms for high issue rates
TL;DR: Results show that compiler optimization can significantly enhance performance across all schemes and the collapsing buffer supplemented by compiler techniques remains the best-performing mechanism.
Proceedings ArticleDOI
Wrong-path instruction prefetching
Jim Pierce,Trevor Mudge +1 more
TL;DR: wrong-path prefetching performs better than the other prefetch algorithms studied in all of the cache configurations examined while requiring little additional hardware and is applicable to both multi-issue and long L1 miss latency machines.
Proceedings ArticleDOI
Instruction fetch mechanisms for VLIW architectures with compressed encodings
TL;DR: This report uses the TINKER experimental testbed to examine instruction fetch and instruction cache mechanisms for VLIWs and a new i-fetch mechanism using a silo cache is found to have the best performance.
References
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Proceedings ArticleDOI
An analysis of MIPS and SPARC instruction set utilization on the SPEC benchmarks
TL;DR: Although MIPS and SPARC each have strengths and weaknesses in their compilers and library routines, the combined effect of compilers or library routines does not give either MIPS or SPARC a clear advantage in these areas.
Journal ArticleDOI
The i486 CPU: executing instructions in one clock cycle
TL;DR: The author discusses the design goals of the i486 development program, which were to ensure binary compatibility with the 386 microprocessor and the 387 math coprocessor, increase performance by two to three times over a 386/387 processor system at the same clock rate, and extend the IBM PC standard architecture of the 386 CPU with features suitable for minicomputers.
Proceedings ArticleDOI
The Intel386 CPU family-architecture and performance analysis
T. Chadha,P. Srinivasan +1 more
TL;DR: The authors present a synopsis of the various performance metrics related to the i386 CPU architecture, and shows how an average number like CPI can vary over the run time of the job.