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Proceedings ArticleDOI

Area - time - power and design effort: the basic tradeoffs in application specific systems

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TLDR
The search for flexibility in design without paying a significant area - time - power cost remains the primary problem for application specific and system on a chip (SoC) design.
Abstract
Application specific is always a tradeoff among competing design goals (or design parameters). In addition to the well established area (cost) - time (performance) - power metrics specific applications imply a relatively limited market so design cost becomes an especially important consideration. As technology offers increasing transistor density with lower cost power constraints limit frequency as the primary avenue to performance. The alternative is to use area (transistors) to recover performance putting an additional strain on the design budget. The search for flexibility in design without paying a significant area - time - power cost remains the primary problem for application specific and system on a chip (SoC) design.

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Proceedings ArticleDOI

A reconfigurable design-for-debug infrastructure for SoCs

TL;DR: A distributed reconfigurable fabric inserted at RTL provides a debug platform that can be configured and operated post-silicon via the JTAG port and can be repeatedly reused to configure many debug structures such as assertions checkers, transaction identifiers, triggers, and event counters.
Proceedings ArticleDOI

Evaluation and design trade-offs between circuit-switched and packet-switched NOCs for application-specific SOCs

TL;DR: The experimental results show that the area, latency and the energy consumption of the packet-switched NOC are much larger than that of the circuit-switches NOC for application-specific designs, and the advocate using circuit- Switched Noc as it is more attractive forApplication-specific SOC designs because of communication localization.
Journal ArticleDOI

Paradigm Shift in Big Data SuperComputing: DataFlow vs. ControlFlow

TL;DR: This paper presents eight recent implementations of various algorithms using the DataFlow paradigm, which show considerable speed-ups, power reductions and space savings over their implementation using the ControlFlow paradigm.
Journal ArticleDOI

New benchmarking methodology and programming model for big data processing

TL;DR: This paper presents one possible solution for the coming exascale big data processing: a data flow computing concept, which integrates the performance issues of speed, area, and power needed to execute the task.
Journal ArticleDOI

Tailoring circuit-switched network-on-chip to application-specific system-on-chip by two optimization schemes

TL;DR: A circuit-switched interconnection architecture which uses crossroad switches to construct dedicated channels dynamically between any pairs of cores for nonhuge application-specific SoCs and can be further reduced approximately 25% by applying partially dedicated path mechanism.
References
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Journal ArticleDOI

Microprocessor design issues: thoughts on the road ahead

TL;DR: A look at the technology roadmap and what it means to computer architects, updating the authors' views of six years ago.
Journal ArticleDOI

Deep submicron microprocessor design issues

TL;DR: Deep-submicron technology allows billions of transistors on a single die, potentially running at gigahertz frequencies, but physical and program behavioral constraints will limit the usefulness of this complexity.
Journal ArticleDOI

Predicting CMOS speed with gate oxide and voltage scaling and interconnect loading effects

TL;DR: In this article, the optimal gate oxide thickness for different interconnect loading was analyzed at supply voltages of 1.5-3.3 V. I/sub dsat/ can be accurately predicted from a universal mobility model and a current model considering velocity saturation and parasitic series resistance.