Patent
Arithmetic unit for carrying out both multiplication and addition in an interval for the multiplication
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TLDR
In this paper, an arithmetic unit comprising a partial product circuit for calculating a plurality of partial products for two numbers and a Wallace tree responsive to the partial products is presented, where an addend is supplied to the Wallace tree as an additional partial product.Abstract:
In an arithmetic unit comprising a partial product circuit for calculating a plurality of partial products for two numbers and a Wallace tree responsive to the partial products for producing a plurality of tree outputs which gives a total product of the two numbers when summed up, an addend is supplied to the Wallace tree as an additional partial product. The arithmetic unit produces a resultant sum of the total product plus the addend. The addend may be supplied to the Wallace tree from one or more registers therefor. Alternatively, a result register is used for the total product with the total product supplied to the Wallace tree as the addend. As a further alternative, an additional register is used for a third number which is used with bit shifts as the addend. In this last event, the arithmetic unit preferably produces a sum selected from the resultant sum.read more
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References
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Journal ArticleDOI
A Suggestion for a Fast Multiplier
TL;DR: A design is developed for a multiplier which generates the product of two numbers using purely combinational logic, i.e., in one gating step, using straightforward diode-transistor logic.
Patent
Digital processing circuit having a multiplication function
TL;DR: In this article, the multiplicand and the multiplier are multiplied by each other to produce a partial product, and the obtained partial products are added to the sum of previously obtained products.
Patent
High-speed multiplier having carry-save adder circuit
TL;DR: In this paper, a carry save adder circuit was proposed for VLSI with a regularly arranged structure having a reduced number of addition stages, where a time difference is imparted to signals input to full adders, in order to eliminate extra wait time in the signal propagation.
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A digital circuit performing an arithmetic operation with an overflow
TL;DR: In this paper, a shifter is used to shift a result of an arithmetic operation with an overflow and to shift the data to be operated by an arithmetic unit via a multiplexer, and either one of them is transferred to the shifter.
Patent
Digital system for computation of the values of composite arithmetic expressions
TL;DR: In this paper, a digital system for computing of the values of composite arithmetic expressions, such as where N, K 1, K 2,....., K N are ARBITRARY INTEGERS, on NUMBERS X IJ in a binary system for application in large computer systems, with the possibility of a collision-free MULTITASK work with multiple computers.
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