Automatic gate-level synthesis of speed-independent circuits
Peter A. Beerel,Teresa H. Meng +1 more
- pp 581-586
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TLDR
This work demonstrates that direct synthesis of gate-level speed-independent circuits is not only feasible, but also produces robust and relatively efficient circuits compared to those synthesized with timing constraints.Abstract:
In this paper, we present a CAD tool for the synthesis of asynchronous control circuits using basic gates such as AND gates and OR gates. The synthesized circuits are speed-independent; that is, they work correctly regardless of individual gate delays. We present synthesis results for a variety of specifications taken from industry and previously published examples. We compare our speed-independent circuits with those non-speedindependent circuits synthesized using the algorithms described in [I], in which delay elements are added to remove circuit hazardr. These synthesis results show that our circuits are on average approximately 25% faster with an area penalty of only IS%. This work demonstrates that direct synthesis of gate-level speed-independent circuits is not only feasible, but also produces robust and relatively efJrcient circuits compared to those synthesized with timing constraints.read more
Citations
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Journal ArticleDOI
Asynchronous design methodologies: an overview
TL;DR: This work examines the benefits and problems inherent in asynchronous computations, and in some of the more notable design methodologies, which include Huffman asynchronous circuits, burst-mode circuits, micropipelines, template-based and trace theory-based delay-insensitive circuits, signal transition graphs, change diagrams, and complication-based quasi-delay-insensitivity circuits.
Journal ArticleDOI
Theory of latency-insensitive design
TL;DR: The theory of latency-insensitive design is presented as the foundation of a new correct-by-construction methodology to design complex systems by assembling intellectual property components to design large digital integrated circuits by using deep submicrometer technologies.
Proceedings ArticleDOI
A methodology for correct-by-construction latency insensitive design
TL;DR: A new synthesis methodology for synchronous systems that makes the design functionally insensitive to the latency of long wires is proposed as well as a report on the latency insensitive design of PDLX, an out-of-order microprocessor with speculative-execution.
Journal ArticleDOI
Applications of asynchronous circuits
TL;DR: A comparison with synchronous circuits suggests four opportunities for the application of asynchronous circuits: high performance, low power; improved noise and electromagnetic compatibility properties, and a natural match with heterogeneous system timing.
Journal ArticleDOI
Synthesis of timed asynchronous circuits
Chris J. Myers,Teresa H. Meng +1 more
TL;DR: The authors present a systematic procedure for synthesizing timed asynchronous circuits using timing constraints dictated by system integration, thereby facilitating natural interaction between synchronous and asynchronous circuits.
References
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Book
Trace Theory for Automatic Hierarchical Verification of Speed-Independent Circuits
TL;DR: The problem of receptiveness is proved to be decidable, by reduction to Church's solvability problem, and the resulting verification methodology is naturally hierarchical, because specifications at one level of abstraction can be used as descriptions at higher levels of abstraction.
Dissertation
Synthesis of self-timed vlsi circuits from graph-theoretic specifications
TL;DR: This thesis presents an approach for direct and efficient synthesis of self-timed (asynchronous) control circuits from formal specifications called Signal Transition Graphs (STGs), and develops a number of analytical results which establish the equivalence between the static structure of nets and their underlying firing sequence semantics.
Journal ArticleDOI
Synthesis of timed asynchronous circuits
Chris J. Myers,Teresa H. Meng +1 more
TL;DR: The authors present a systematic procedure for synthesizing timed asynchronous circuits using timing constraints dictated by system integration, thereby facilitating natural interaction between synchronous and asynchronous circuits.
Proceedings ArticleDOI
Algorithms for synthesis of hazard-free asynchronous circuits
TL;DR: Algorithms for synthesis and hazard removal are given, able to produce hazard-free circuits with the bounded wire-delay model, requiring the STG to be live, safe and to have the unique state coding property.