Automatic insertion of BIST hardware using VHDL
Kwanghyun Kim,Joseph G. Tront,Dong Sam Ha +2 more
- pp 9-15
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TLDR
A system which automatically inserts BIST hardware to a circuit described in VHDL (VHSIC Hardware Description Language) and the use of BILBO (built-in logic block observer) is primarily pursued in the system.Abstract:
A system is presented which automatically inserts BIST (built-in self-testing) hardware to a circuit described in VHDL (VHSIC Hardware Description Language). An appropriate VHDL modeling style for automatic insertion of BIST hardware is investigated. The use of BILBO (built-in logic block observer) is primarily pursued in the system. Algorithmic and rule-based approaches are used in the insertion of BILBO. Test scheduling and control signal distribution are also performed by the system. >read more
Citations
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Proceedings ArticleDOI
I-path analysis
TL;DR: It is shown, how the graph theory algorithms can be used to derive the information about the accessibility of circuit components, i.e., the existence of I-paths between them, and the sequences of control and clock signals which must be generated to transfer the information along the existing I- Paths.
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A VHDL primer
TL;DR: VHDL-93 features,Packages and Libraries, Generics and Configurations, Subprograms and Subprogram Overloading, and More on Ports.
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A data path synthesis method for self-testable designs
TL;DR: A high level synthesis for testability method is presented whose objective is to generate self-testable RTL designs from data flow behavioral descriptions based on an underlying structural testability model and its connection rules.
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A powerful global router: based on Steiner min-max trees
TL;DR: A study is made of the global routing of multiterminal nets, and an efficient algorithm is presented for obtaining a Steiner min-max tree, in a weighted graph.
Proceedings ArticleDOI
A built-in self-testing approach for minimizing hardware overhead
S. Chiu,Christos A. Papachristou +1 more
TL;DR: A built-in self-test (BIST) hardware insertion technique is addressed, applying to register transfer level designs, that utilizes not only the circuit structure but also the module functionality in reducing test hardware overhead.
References
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TL;DR: The basis of this book is the material contained in the first six chapters of the earlier work, The Design and Analysis of Computer Algorithms, and has added material on algorithms for external storage and memory management.
Journal ArticleDOI
A Knowledge-Based System for Designing Testable VLSI Chips
Magdy S. Abadir,Melvin A. Breuer +1 more
TL;DR: This article describes efforts to build a knowledge-based expert system for designing testable VLSI chips and introduces a framework for a methodology incorporating structural, behavioral, qualitative, and quantitative aspects of known DFT techniques.