SLAC - PUB - 3694
May
1985
(A)
BINARY PEAK-POWER MULTIPLIER AND
ITS APPLICATION TO LINEAR ACCELERATOR DESIGN*
Z.
D.
FARKAS
Stanford Linear Accelerator Center
Stanford University, Stanford, California, 94305
ABSTRACT
The voltage gained by a charged particle traversing an accelerator section is
proportional to the peak power into the section. Thus a high peak power
results
in high particle voltages in a relatively short distance, a practical requirement
of high particle energy accelerators. Pulse compression is a means to obtain
high peak power. This note describes a new method of pulse compression, the
Binary Power Multiplier, (BPM) a device which multiplies rf power in binary
steps. It comprises one or more stages, each of which doubles the input power
and halves the input pulse length.
Thus the BPM increases peak power by
multiples of 2 by means of pulse compression. The active control element of
the binary power multiplier operates at low power and only passive devices are
needed in the high power portion. We will describe practical designs and derive
the expression for their compression efficiency. We will illustrate the usefulness of
pulse compression for accelerator design and compare accelerator power systems
using the binary power multiplier with the pulse compression system currently
in use at the Stanford Linear Accelerator Center.
Submitted to Special Transaction Issue on
New and Future Applications of Microwave Systems
* Work supported by the Department of Energy, contract DE -
AC03 - 76SF00515.
INTRODUCTION
The voltage gained by a charged particle traversing an accelerator section
divided by the section length, the average gradient, varies as the peak power
amplitude into the section.
High gradients are especially important for a new
type of electron-positron collider, the linear collider,’ where two linear acceler-
ators produce particle beams which are bought into collision once and then are
discarded. This new type collider is more efficient at high particle energies than
an electron-positron storage ring.
The first attempt to achieve electron positron-collisions with a linear collider
is the Stanford Linear Collider’ (SLC)
p resently nearing completion at Stanford
Linear Accelerator Center (SLAC). While not a true linear collider (the SLC uses
the SLAC accelerator to inject electrons and positrons into two arcs which bend
the beams into collision), it will nonetheless serve the dual purpose of a unique
physics tool and a demonstration of some aspects of linear collider technology.
Proposed future positron-electron colliders3 would be capable of investigating
fundamental processes of interest in the l-5 TeV beam energy range. At the SLC
gradient of about 21 MV/m this would imply prohibitive lengths of about 50-250
kilometers per linac.
We can reduce the length by increasing the gradient but
this implies high peak power. Using the SLAC accelerator sections, operating at
2856 MHz, a 100 MV/m gradient requires 750 MW peak power.
Another requiremert of Multi-TeV colliders is high average power. For a
given gradient, both peak and average powers depend on section fill time. The
peak power increases as we decrease the fill time from its value where the peak
power has a broad minimum.
On the other hand the average power decreases
monotonically as the fill time is decreased.
Thus we can reduce the average
power at the expense of increased peak power. We can trade higher peak power
for lower average power. Pulse compression is a means to obtain high peak power.
It adapts the relatively long source pulse length to the relatively short accelerator
section fill time. If we can compress with nearly 100% efficiency we can increase
2
peak power without increasing average power.
To produce the unloaded 21 MV/m SLC gradient which requires 160 MW
peak power SLAC uses a compression system SLED4 which compresses a 50 MW
5 ps klystron pulse into an effective 160 MW 0.82 ps pulse. (The fill time of the
SLAC accelerator section is 0.82 1~s). SLED has the following shortcomings. Its
maximum efficiency of 81% can only be reached at a compression ratio of about
3:1, and drops off sharply as the compression ratio deviates from 3:l. Moreover,
the compressed pulse varies with time, which reduces the efficiency when it is
used as the power input to an accelerator section. With the BPM we have a
rectangular (flat) output pulse and if we reduce dissipation we can approach
100% efficiency. In its high power portion the BPM has only delay lines and
3dB couplers which are capable of carrying very high peak power. 3 dB side wall
couplers tested at SLAC at 2856 MHz did not break down at peak power levels
in excess of 500MW.
GENERAL DESCRIPTION OF THE BPM
The Binary Power Multiplier (BPM) includes a front-end, a pair of high power
amplifiers (klystrons), and one or more compression stages. Refer to Figure 1.
The front-end consists of a power splitter and two biphase modulators which code
the klystron inputs in time bins equal to the final compressed pulse length with
either zero or 180’ phase shift. The phase changes must occur in an interval short
compared to the compressed pulse length. The klystron outputs are connected
to one or more pulse compression stages.
Each stage consists of a 3 dB hybrid
with one output port connected to a delay line whose delay is half the input pulse
length and the other output port connected to zero delay transmission line. Each
stage converts its two coded inputs into two outputs whose power amplitudes are
twice that of the two input amplitudes, and are appropriately coded for the next
stage. An n stage BPM starts with two klystron pulses of unity power amplitude
and 2n duration in units of the compressed pulse length, and ends up with two
3
pulses of 2n power amplitude and unity pulse length, assuming lossless delay
lines. The active control elements of the BPM, the biphase modulators that do
the coding, operate at low powe;, and only passive devices are needed in the high
power portion of the BPM. The BPM can also transform a continuous wave input
into a train of pulses although the output duty cycle is constrained to discrete
values (powers of 2).
SINGLE STAGE BPM
Because of its simplicity we explain first the operation of a single stage BPM
which consists of a front-end and a single compression stage as shown in Fig. 1.
The low level output of a single source is divided by the 3 dB coupler Hi to drive
two high power klystrons Ka and Kb. Each pulse duration is determined by the
klystron modulators Ma and Mb and is set to twice the compressed pulse length.
The biphase modulator & codes the two klystron outputs as shown at (b) and
(d) in Fig. 1. Here a plus sign indicates zero phase and a minus sign indicates a
phase shift of 180’. Tim.e is in units of the compressed output pulse length. The
function of phase shifter &, (not coded) is to ensure that the klystron outputs are
precisely in phase or 180’ out of phase. The two klystron outputs are connected
to the two inputs of the 3 dB coupler H. The properties of the 3dB hybrid (with
properly chosen reference planes) are such that if the phase of between the two
inputs is zero the combined power appears at terminal 01 and when the phase
is 180’ the combined power appears at 02. Terminal 01 of the hybrid H is
connected to the delay line D whose time delay is the compressed pulse length.
After a time interval equal to one half the input pulse duration the phase shift of
biphase modulator &, is changed by 180'.
As a consequence, during the second
half of the input pulse the combined output of the two klystrons exits terminal
02 of the hybrid. As the rf at terminal 01 is delayed by half the pulse duration
the two outputs appear simultaneously at the two outputs of the BPM. The two
klystron pulses are transformed into two output pulses; the duration of each pulse
is one half and the peak power is double the output of a single klystron.
4
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Figure 1. Diagram of a single stage BPM.