Journal ArticleDOI
Cache-based Computer Systems
K.R. Kaplan,R.O. Winder +1 more
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TLDR
A cache-based computer system employs a fast, small memory interposed between the usual processor and main memory that provides a smaller ratio of memory access times, and holds the processor idle while blocks of data are being transferred from main memory to cache rather than switching to another task.Abstract:
A cache-based computer system employs a fast, small memory -the " cache" - interposed between the usual processor and main memory. At any given time the cache contains as much as possible the instructions and data the processor needs; as new information is needed it is brought from main memory to cache, displacing old information. The processor tends to operate with a memory of cache speed but with main memory cost-per-bit. This configuration has analogies with other systems employing memory hierarchies, such as "paging" or "virtual memory" systems. In contrast with these latter, a cache is managed by hardware algorithms, deals with smaller blocks of data (32 bytes, for example, rather than 4096), provides a smaller ratio of memory access times (5:1 rather than 1000: 1), and, because of the last factor, holds the processor idle while blocks of data are being transferred from main memory to cache rather than switching to another task. These are important differences, and may suffice to make the cache-based system cost effective in many situations where paging is not.read more
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Journal ArticleDOI
Cache Memories
TL;DR: Specific aspects of cache memories investigated include: the cache fetch algorithm (demand versus prefetch), the placement and replacement algorithms, line size, store-through versus copy-back updating of main memory, cold-start versus warm-start miss ratios, mulhcache consistency, the effect of input /output through the cache, the behavior of split data/instruction caches, and cache size.
Journal ArticleDOI
The NYU Ultracomputer—Designing an MIMD Shared Memory Parallel Computer
TL;DR: The design for the NYU Ultracomputer is presented, a shared-memory MIMD parallel machine composed of thousands of autonomous processing elements that uses an enhanced message switching network with the geometry of an Omega-network to approximate the ideal behavior of Schwartz's paracomputers model of computation.
Journal ArticleDOI
Evaluating associativity in CPU caches
Mark D. Hill,Alan Jay Smith +1 more
TL;DR: All-associativity simulation is theoretically less efficient than forest simulation or stack simulation (a commonly used simulation algorithm), in practice it is not much slower and allows the simulation of many more caches with a single pass through an address trace.
Proceedings ArticleDOI
A low-overhead coherence solution for multiprocessors with private cache memories
TL;DR: This paper presents a cache coherence solution for multiprocessors organized around a single time-shared bus that aims at reducing bus traffic and hence bus wait time and increases the overall processor utilization.
Proceedings ArticleDOI
Lockup-free instruction fetch/prefetch cache organization
TL;DR: A cache organization is presented that essentially eliminates a penalty on subsequent cache references following a cache miss and has been incorporated in a cache/memory interface subsystem design, and the design has been implemented and prototyped.
References
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Journal ArticleDOI
Structural aspects of the system/360 model 85: II the cache
TL;DR: The cache, a high-speed buffer establishing a storage hierarchy in the Model 85, is discussed in depth in this part, since it represents the basic organizational departure from other SYSTEM/360 computers.
Journal ArticleDOI
Slave Memories and Dynamic Storage Allocation
TL;DR: The use is discussed of a fast core memory of, say, 32000 words as a slave to a slower core memory in such a way that in practical cases the effective access time is nearer that of the fast memory than that ofThe slow memory.
Proceedings ArticleDOI
Considerations in block-oriented systems design
TL;DR: The feasibility of transmitting blocks of words between memory and CPU is explored in a simulation model driven by customer-based IBM 7000 series data, and block transfer is seen to be an efficient memory access method which can provide high performance, superior to single-word access.
Journal ArticleDOI
Evaluation of multilevel memories
TL;DR: Stack processing is described as a replacement for simulation that obtains hit-ratio data 1000 times faster than before and an example is given to illustrate how to select between two competing technologies, how to design the best hierarchy, and how to determine the information flow which optimizes the total cost performance of the system.