Proceedings ArticleDOI
Challenges in Large FPGA-based Logic Emulation Systems
William N. N. Hung,Richard Yachyang Sun +1 more
- pp 26-33
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TLDR
This paper focuses on commercial FPGA based logic emulation and presents various challenging problems in this area for the academic community.Abstract:
Functional verification is an important aspect of electronic design automation. Traditionally, simulation at the register transfer-level has been the mainstream functional verification approach. Formal verification and various static analysis checkers have been used to complement specific corners of logic simulation. However, as the size of IC designs grow exponentially, all the above approaches fail to scale with the design growth. In recent years, logic emulation have gained popularity in functional verification, partly due to their performance and scalability benefits. There are two main approaches to logic emulation: ASIC and commercial field-programmable gate array (FPGA). In this paper, we focus on commercial FPGA based logic emulation and present various challenging problems in this area for the academic community.read more
Citations
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Proceedings ArticleDOI
Simultaneous partitioning and signals grouping for time-division multiplexing in 2.5D FPGA-based systems
TL;DR: Experimental results show that the proposed simultaneous partitioning and grouping algorithm outperforms the state-of-the-arts flow in both cross-die signal timing criticality and system-clock periods.
Proceedings ArticleDOI
Golden Gate: Bridging The Resource-Efficiency Gap Between ASICs and FPGA Prototypes
TL;DR: Golden Gate is presented, an FPGA-based simulation tool that decouples the timing of anFPGA host platform from that of the target RTL design, and LIME, a model-checking tool that provides a push-button flow for checking whether optimized subcomponents adhere to an associated correctness specification, while also guaranteeing forward progress.
Proceedings ArticleDOI
An Analytical Approach for Time-Division Multiplexing Optimization in Multi-FPGA based Systems
TL;DR: To optimize system clock period effectively and efficiently, a two-step analytical framework is proposed, which first gives a continuous result using a non-linear conjugate gradient-based method and then finalizes the result optimally by a dynamic programming-based discretization algorithm.
Proceedings ArticleDOI
Towards Developing High Performance RISC-V Processors Using Agile Methodology
Yinan Xu,Zi Bo Yu,Dan Tang,Guokai Chen,Lu Chen,Lingrui Gou,Yue Jin,Qianruo Li,Xin Li,Zuojun Li,Jiawei Lin,Tony Liu,Zhigang Liu,Jiazhan Tan,Huaqiang Wang,Huizhe Wang,Kaifan Wang,Chuanqi Zhang,Fa Chao Zhang,Linjuan Zhang,Zifei Zhang,Yang Zhao,Yaoyang Zhou,Yike Zhou,Jiangrui Zou,Ye Cai,Dan-Dan Huan,Zusong Li,Jiye Zhao,Zihao Chen,Wei Sheng He,Qiyuan Quan,Xingwu Liu,Sa Wang,Kan Shi,Ninghui Sun,Yungang Bao +36 more
TL;DR: MINJIE, an open-source platform supporting agile processor development flow that integrates a broad set of tools for logic design, functional verification, performance modelling, pre-silicon validation and debugging for better development efficiency of state-of-the-art processor designs is proposed.
Proceedings ArticleDOI
Time-Division Multiplexing Based System-Level FPGA Routing for Logic Verification*
TL;DR: This paper proposes a TDM-based system-level routing algorithm to simultaneously minimize the maximum TDM (signal multiplexing) ratio and runtime, considering the crucial ratio constraints, and achieves the best runtime and TDM ratio while satisfying all TDM constraints.
References
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