Proceedings ArticleDOI
CirKet: A Performance Efficient Hybrid Switching Mechanism for NoC Architectures
Mohamad FallahRad,Ahmad Patooghy,Hesamedin Ziaeeziabari,Ebadollah Taheri +3 more
- pp 123-130
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TLDR
Results show that the proposed switching mechanism offers at least 10% improvement in overall flit latency in all tested scenarios as compared with a packet-switched NoC, reduces the power dissipation in the router logic by at least 4%, and imposes a negligible area overhead to NoC router circuitry.Abstract:
In this paper, we propose and evaluate a hybrid switching mechanism for Network-on-Chips (NoCs) We propose the use of pseudo circuit-switching along with packet-switching in NoC routers To do this, packets traversing NoC channels are categorized into high and low priority packets which are routed using pseudo circuit and packet switching respectively Each output port of NoC routers are equipped with a one-bit flag register indicating that the traversing packet is either of low or high priority packet Using pseudo circuit switching, high priority packets reserve the intermediate routers till the tail flit passes the router The proposed switching mechanism offers its highest efficiency for applications in which the traffic is dominated by streams We have used Booksim2 which is a cycle accurate NoC simulator to evaluate the proposed switching technique Results show that the proposed switching mechanism 1) offers at least 10% improvement in overall flit latency in all tested scenarios as compared with a packet-switched NoC, 2) reduces the power dissipation in the router logic by at least 4%, and 3) imposes a negligible area overhead to NoC router circuitryread more
Citations
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Journal ArticleDOI
Evaluation of low power consumption network on chip routing architecture
Arulananth T S,M. Baskar,Udhaya Sankar S M,R. Thiagarajan,Arul Dalton G,Pasupuleti Raja Rajeshwari,Aruru Sai Kumar,A. Suresh +7 more
TL;DR: The proposed High-Speed Virtual Logic Network on Chip router architecture is utilized for controlling the traffic congestion and deadlock issues, reduce the latency by selecting the minimal interval paths, and considers the dynamic congestion and route available to perform routing with the least power consumption.
Journal ArticleDOI
Architectural Techniques for Improving the Power Consumption of NoC-Based CMPs: A Case Study of Cache and Network Layer
TL;DR: This work presents a survey of power-saving techniques for efficient NoC designs with a focus on the cache and router components, such as the buffer and crossbar, to compile a quick reference guide for engineers and researchers.
Proceedings ArticleDOI
A Review on Hybrid Network on Chip
M. Sujatha,R. Jayagowri +1 more
TL;DR: This paper reviews the various NOCs for wired, wireless and hybrid networks also techniques in Nocs that addresses the challenges of deadlock, adaptability of the network, power management, latency reduction and throughput improvement etc.
Book Chapter
A survey of low power techniques for efficient Network-on-Chip design
TL;DR: This paper presents recent contributions and efficient saving techniques at the router, NoC architecture and Communication link level that can reduce power dissipation in NoC routers.
Book ChapterDOI
Performance Analysis of Data Communication Using Hybrid NoC for Low Latency and High Throughput on FPGA
C. Amaresh,Anand Jatti +1 more
TL;DR: This paper proposes the modeling of network architecture in consideration with 8 × 8 switch router which indulges the suitable algorithm for shortest path finder, i.e., minimum spanning tree, for efficient routing in run-time.
References
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Journal ArticleDOI
Networks on chips: a new SoC paradigm
Luca Benini,G. De Micheli +1 more
TL;DR: Focusing on using probabilistic metrics such as average values or variance to quantify design objectives such as performance and power will lead to a major change in SoC design methodologies.
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Interconnection Networks: An Engineering Approach
TL;DR: The book's engineering approach considers the issues that designers need to deal with and presents a broad set of practical solutions that address the challenges and details the basic underlying concepts of interconnection networks.
Proceedings ArticleDOI
A detailed and flexible cycle-accurate Network-on-Chip simulator
Nan Jiang,Daniel U. Becker,George Michelogiannakis,James Balfour,Brian Towles,David E. Shaw,John Kim,William J. Dally +7 more
TL;DR: The simulator, BookSim, is designed for simulation flexibility and accurate modeling of network components and offers a large set of configurable network parameters in terms of topology, routing algorithm, flow control, and router microarchitecture, including buffer management and allocation schemes.
Proceedings ArticleDOI
Trade Offs in the Design of a Router with Both Guaranteed and Best-Effort Services for Networks on Chip
Edwin Rijpkema,Kees Goossens,Andrei Radulescu,John Dielissen,J. van Meerbergen,Paul Wielage,E. Waterlander +6 more
TL;DR: In this article, the guaranteed throughput (GT) and best-effort (BE) routers are combined in an efficient implementation by sharing resources, and the trade offs between hardware complexity and efficiency of the combined router are discussed.
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