Patent
Clock distribution method and apparatus for high speed circuits with low skew using counterpropaging true and complement re-generated clock signals with predetermined ramp shapes
Burnell G. West,Madhukar B. Vora +1 more
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TLDR
In this article, a method and apparatus for distributing high speed clock signals on an integrated circuit while eliminating clock skew is presented, where the signal paths are defined by the user after the integrated circuit leaves the place of manufacture and enables field programmable gate arrays to operate at clock speeds in excess of 200 MHz, a speed not previously attainable.Abstract:
There is disclosed herein a method and apparatus for distributing high speed clock signals on an integrated circuit while eliminating clock skew. The invention is particularly useful in field programmable gate arrays where the signal paths are defined by the user after the integrated circuit leaves the place of manufacture and enables field programmable gate arrays to operate at clock speeds in excess of 200 MHz, a speed not previously attainable. Clock skew is eliminated by generating differential clock signals at each of four corners of the array from master differential clock signal delivered simultaneously to each of the four corners. The differential clock signals generated at each corner have ramps the rise time of which slightly exceeds the propagation delay of a clock signal traversing the array. The true signal is propagated across both the top and bottom of the array of cells in the same direction and the complement clock signal is propagated across both the top and bottom of the array of cells in the opposite direction. At the top and bottom of each column, secondary clock receivers receive the true and complement clock signals and generate new differential column clock signals with ramps that are triggered at the time at each column when the true and complement clock signals "crossover", i.e., are equal in amplitude. The ramps of these column clock signals also have rise times which slightly exceed the propagation delay of a clock signal propagating down a column. The differential clock signals are generated at the top and bottom of each column. The true clock signal generated at the top of each column is propagated down each column and the complement clock signal generated at the bottom of each column is propagated up the column. Each cell uses as its clock marker the crossover point between the counter-propagating true and complement clock signals.read more
Citations
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References
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Patent
Multiphase clock distribution for VLSI chip
Akira Yamagiwa,Toshihiro Okabe +1 more
TL;DR: In this paper, a multi-phase clock signals are delivered to a large number of load circuits scattered on a chip from clock signal input pins through at least three stage buffer circuits, and equal delay times are provided in the clock signal paths from the input pins to the load circuits at the respective phases.
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