Patent
Clock signal supply system
Noboru Masuda,Ryotaro Kamikawai,Masayoshi Yagyu,Masakazu Hitachi Suzuki Shinden Shataku Yamamoto,Hiroyuki Itoh,Tatsuya Saito +5 more
TLDR
In this paper, a clock signal supply system provides an adjusting circuit to adjust the phase of the received clock signals at each location where the clock signal is to be received, and this adjustment is carried out at each of the locations at which the clock signals are to be transmitted.Abstract:
A clock signal supply system provides for automatic accurate phase adjustment of clock signals. The system includes an oscillator that produces clock signals and a reference generator that generates a reference signal that has a predetermined relationship with respect to the clock signals produced by the oscillator. At each location where the clock signal is to be received, an adjusting circuit is provided to adjust the phase of the received clock signals. Such an adjusting circuit may include a variable delay circuit which receives the clock signal and produces an output which is constituted by the clock signal having a varied delay, to the remainder of the attached circuits. Further, the output of the variable delay is fed back to a phase difference detection circuit. The reference signal is second input to the phase difference detection circuit. This phase difference detection circuit compares the difference of the reference signal and the output of the variable delay circuit and produces the control signal to the variable delay circuit which will further adjust the phase of the clock signal that is received. This adjustment is carried out at each of the locations where the clock signal is to be received, thereby providing automatic adjustment of the phase of the clock signals.read more
Citations
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References
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Patent
Digital timing recovery system
TL;DR: In this paper, the clock reference signal is phase matched with the digital data by comparing the positive going and negative going edges of the data with the clocking edge of the clock signal.
Journal ArticleDOI
A synchronous approach for clocking VLSI systems
TL;DR: Presents a synchronous solution for clocking VLSI systems organized as distributed systems to resynchronize the phase of each module clock on the transitions of the communication clock by a phase locked loop circuitry added to each module.
Patent
Clock signal supplying device having a phase compensation circuit
TL;DR: In this paper, a clock signal supplying device with an automatic phase regulating function for preventing errors in the phase regulation due to noise is presented, where a noise filter is provided which detects phase regulation errors to effect correct phase regulation.
Patent
Clock pulse generator with selective pulse delay and pulse width control
TL;DR: In this paper, the registers are located in coarse and fine pulse delay and pulse width adjustment units, which have the same physical structure, but are functionally definable by a settable control element.
Patent
Data processing device
TL;DR: In this paper, a phase correction control circuit is used to detect a phase error between observation points by a storage element, varying a delayed quantity of a variable delay element so that the error is corrected to an allowable value or below, and executing a clock phase adjustment.