Patent
Column redundance circuit configuration for a memory
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TLDR
In this paper, a column redundance circuit for a memory includes a memory blocks with memory cells disposed in x lines and y columns, and a column decoder and c redundant column decoders are provided.Abstract:
A column redundance circuit configuration for a memory includes a memory blocks with memory cells disposed in x lines and y columns. Redundant memory cells are disposed in b lines and c columns. A column decoder and c redundant column decoders are provided. Each column decoder is assigned to a respective one of the c redundant columns of each of the memory blocks. D encoding elements each have an address decoding device for assigning it to an arbitrary memory block.read more
Citations
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Patent
Method for reconfiguring a memory
TL;DR: In this article, the first and second redundant address lines of a memory block are replaced by redundant memory cells, and a fault image is determined and the memory is reconfigured so as to replace faulty memory cells.
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TL;DR: In this article, a redundant circuit for EEPROMs which is capable of replacing defective normal memory cells with redundant memory cells in a wafer state as well as in a packaged state is presented.
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Semiconductor memory device having redundancy function
TL;DR: In this article, a high-density semiconductor memory device may be provided with redundant memory, so that it is capable of repairing defects generated in a normal memory cell array by using a spare memory array which has a plurality of sub memory cell arrays, split word line driver blocks and sense amps.
References
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Patent
A flexible redundancy architecture and fuse download scheme
TL;DR: In this paper, a fuse download system for programming decoders for redundancy is presented, where each set of fuses can be accessed and downloaded to program selected redundant decoder sets on an any-for-any basis.
Patent
Semiconductor memory device having redundant circuit
TL;DR: In this paper, a column redundant circuit (20) is used to select the spare column line (SCDL) and an OR gate (22) is provided to derive the logical sum of outputs of the four spare column decoders (21-1 to 21-4).
Patent
Semiconductor circuit device having multiplex selection functions
Kikuta Shigeru,Hamamoto Takeshi +1 more
TL;DR: In this article, a first column decoder for decoding an internal column address and generating a column select signal which selects one column, and a second columndecoder for simultaneously selecting a plurality of successively adjacent columns from a memory cell array in accordance with the column select signals.
Patent
System with laser link decoder for DRAM redundancy scheme
TL;DR: In this paper, a decoder for a memory redundancy scheme is presented, which allows replacement of a number of memory cell locations in connection with the state of a plurality of fuses.