Comparative analysis of different AES implementation techniques for efficient resource usage and better performance of an FPGA
Umer Farooq,M. Faisal Aslam +1 more
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TLDR
This work proposes a technique based on optimized implementation of AES on FPGA by making efficient resource usage of the target device, which has 32% higher frequency, while consuming 2.63 more slice LUTs, 8.33 less slice registers, and 12.59 less LUT-FF pairs.About:Â
This article is published in Journal of King Saud University - Computer and Information Sciences.The article was published on 2017-07-01 and is currently open access. It has received 45 citations till now. The article focuses on the topics: AES implementations & Advanced Encryption Standard.read more
Citations
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Journal ArticleDOI
An efficient AES implementation using FPGA with enhanced security features
Harshali Zodpe,Ashok M. Sapkal +1 more
TL;DR: A new approach for generating S-box values and initial key required for encryption/encryption (improved key generation) using PN Sequence Generator and the AES algorithm with proposed modifications shows significant improvement in the encryption quality as compared to traditional AES algorithm.
Journal ArticleDOI
A Low Area High Speed FPGA Implementation of AES Architecture for Cryptography Application
Thanikodi Manoj Kumar,Kasarla Satish Reddy,Stefano Rinaldi,Bidare Divakarachari Parameshachari,Kavitha Arunachalam +4 more
TL;DR: Low power high-speed hardware architectures for the efficient field programmable gate array (FPGA) implementation of the advanced encryption standard (AES) algorithm to provide data security and modified positive polarity reed muller (MPPRM) architecture is inserted.
Journal ArticleDOI
High performance FPGA based secured hardware model for IoT devices
Anurag Shrivastava,D. Haripriya,Yogini Borole,Archana S. Nanoty,Charanjeet Singh,Divyanshu Chauhan +5 more
Journal ArticleDOI
Efficient adaptive framework for securing the Internet of Things devices
TL;DR: This work formulated a weighted optimization problem to secure the IoT devices of heterogeneous nature while finding the best trade-off between their resource usage and throughput, and proposes a novel adaptive framework that adaptively secures the IoT-based system while providing better resource used and throughput results.
Journal ArticleDOI
A lightweight AES algorithm implementation for encrypting voice messages using field programmable gate arrays
TL;DR: This paper gives an idea of encrypting voice signals over peer to peer communication with the help of a modified and lightweight AES algorithm that is similar to the traditional AES algorithm in most of the aspects but does not imply the use of mix column that is used in theTraditional AES algorithm.
References
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Book
Cryptography and Network Security: Principles and Practice
TL;DR: The new edition of William Stallings' Cryptography and Network Security: Principles and Practice, 5e is a practical survey of cryptography and network security with unmatched support for instructors and students.
Proceedings ArticleDOI
Measuring the gap between FPGAs and ASICs
Ian Kuon,Jonathan Rose +1 more
TL;DR: Experimental measurements of the differences between a 90- nm CMOS field programmable gate array (FPGA) and 90-nm CMOS standard-cell application-specific integrated circuits (ASICs) in terms of logic density, circuit speed, and power consumption for core logic are presented.
Book ChapterDOI
The Block Cipher Rijndael
Joan Daemen,Vincent Rijmen +1 more
TL;DR: The block cipher Rijndael as mentioned in this paper is one of the fifteen candidate algorithms for the Advanced Encryption Standard (AES) and can be implemented very efficiently on smart cards.
Journal ArticleDOI
An FPGA-based performance evaluation of the AES block cipher candidate algorithm finalists
TL;DR: This contribution investigates the significance of FPGA implementations of the Advanced Encryption Standard candidate algorithms, with a strong focus on high-throughput implementations, which are required to support security for current and future high bandwidth applications.
Proceedings ArticleDOI
Compact and efficient encryption/decryption module for FPGA implementation of the AES Rijndael very well suited for small embedded applications
TL;DR: This work purpose an efficient solution to combine Rijndael encryption and decryption in one FPGA design, with a strong focus on low area constraints, which fits into the smallest Xilinx FPGAs, deals with data streams of 208 Mbps, and improves by 68% the best-known similar designs in terms of ratio Throughput/Area.
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