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Patent

Complementary MOS inverter structure

TLDR
In this paper, a complementary MOS inverter includes transistors each of which has a dual gate structure with the threshold voltage of the channel nearest the drain of each transistor arranged to be lower than that of the source of each transistor.
Abstract
A complementary MOS inverter includes transistors each of which has a dual gate structure with the threshold voltage of the channel nearest the drain of each transistor arranged to be lower than that of the channel nearest the source of each transistor. This arrangement provides the cascode characteristics of dual gate structure, i.e., high breakdown voltage, high voltage gain, low drain output conductance, and relatively fast frequency response, but allows all four gate electrodes of the transistors to be connected in common, thus enabling relatively simple layout.

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Citations
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Patent

Process for making integrated circuits having titanium nitride triple interconnect

TL;DR: Disclosed is a process for making VLSI integrated circuits and a local interconnect system, wherein first poly, second poly and moat are all interconnected in any desired pattern by a TiN local interconnection as mentioned in this paper.
Patent

SRAM with local interconnect

TL;DR: In this article, an SRAM using TiN local interconnects was proposed to reduce the moat parasitic capacitance and avoid the use of metal jumpers, resulting in increased density.
Patent

Integrated circuit device and process with tin capacitors

TL;DR: In this paper, a new integrated circuit structure was proposed, where a TiN thin film layer was separated by a thin dielectric to define capacitors, at various other locations, the TiN layers also made contact to the polysilicon layer, and also provided a contact pad for a third patterned thin film conductor layer which overlies the other two.
Patent

VLSI local interconnect structure

TL;DR: In this paper, a local interconnect system for VLSI integrated circuits is presented, which allows contacts to be misaligned with the moat boundary, since the titanium nitride local interfconnect layer can be overlapped from the exposed moat up on to the field oxide to provide a bottom contact and diffusion barrier for a contact hole which is subsequently etched through the interlevel oxide.
Patent

VLSI interconnect method and structure

TL;DR: In this article, a local interconnect system for VLSI integrated circuits is presented, which allows contacts to be misaligned with the moat boundary, since the titanium nitride local interfconnect layer can be overlapped from the exposed moat up on to the field oxide to provide a bottom contact and diffusion barrier for a contact hole which is subsequently etched through the interlevel oxide.
References
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Patent

Process for preparing a substrate for mos devices of different thresholds

TL;DR: In this article, a process for forming a plurality of host regions of different conductivity types and dopant concentration levels is described, which include the channels of MOS field effect devices, thereby providing devices of different voltage thresholds.
Patent

Method for forming a narrow channel length MOS field effect transistor

TL;DR: In this article, an N-channel silicon MOS field effect transistor on a P-type substrate is fabricated by using ion implantation to create an N type surface layer in the channel and then overcompensating this layer to create a P type region near the source by ion implanting P type ions into the source junction region.
Patent

Method for making FET circuits

TL;DR: An integrated circuit and process for manufacturing the same is disclosed in this paper, which comprises both depletion and enhancement mode field effect transistors, each having silicon gates and self-aligned gate regions.
Patent

Asymmetrical dual-gate FET

TL;DR: In this paper, a dual-gate FET is described where the second channel is made more conductive than the first such that when employed as an amplifier or a mixer circuit, zero bias is required from the gates to ground.