scispace - formally typeset
Journal ArticleDOI

Computer-Aided 3D ICs Layout Design

TLDR
A new framework for visual kind of intelligent layout design is presented, where a shape grammar generates possible design solutions while intelligent algorithms control the direction of the solution space exploration.
Abstract
Computer-aided 3D ICs layout design requires efficient search of large and discontinuous spaces and no deterministic algorithms are able to perform such a task. The paper presents a new framework for visual kind of intelligent layout design. In the proposed approach a shape grammar generates possible design solutions while intelligent algorithms control the direction of the solution space exploration. Although the method is not limited to a particular design assignment, the paper focuses on a 3D ICs layout problem to demonstrate its potential.

read more

Citations
More filters
Journal ArticleDOI

Using shape grammars and extremal optimization in 3D IC layout design

TL;DR: The paper focuses on the post-generation 3D IC wirelength optimization stage, and the original partitioning heuristics implemented by the means of the extremal optimization is applied to the MCNC set of benchmark circuits.
Journal ArticleDOI

Hypergraphs and extremal optimization in 3D integrated circuit design automation

TL;DR: The paper presents a knowledge intensive 3D ICs layout hypergraph representation together with the elaborated neighborhood optimization heuristics and the results of the Extremal Optimization (EO) implementation applied to the MCNC set of benchmark circuits are reported.
Proceedings ArticleDOI

Extremal optimization approach to 3D design of integrated circuits layouts

TL;DR: This paper presents an original 3D layout graph partitioning heuristics implemented with the use of extremal optimization method and the preliminary results show very good performance and stimulate further research.
Book ChapterDOI

Emergent Phenomena in Constrained 3D Layout Design

TL;DR: This paper presents the original approach to constrained 3D component layout design problem that takes advantage of visual shape grammar computations, emergent phenomena and computational intelligence methods.
Book ChapterDOI

3D Integrated Circuits Layout Optimization Game

TL;DR: This paper is devoted to the original approach to block-level 3D IC layout design, where the circuit components are modeled as autonomous mobile agents that explore their virtual world in order to find a globally near-optimal layout solution.
References
More filters
Journal ArticleDOI

Procedural modeling of buildings

TL;DR: CGA shape is shown to efficiently generate massive urban models with unprecedented level of detail, with the virtual rebuilding of the archaeological site of Pompeii as a case in point.
Journal ArticleDOI

Introduction to Shape and Shape Grammars

TL;DR: This paper takes a whirlwind tour through the shape grammar formalism, and the definitions and ideas on which it is based, and establishes the formal machinery for the algorithmic definition of languages of two and three-dimensional spatial designs.
Journal ArticleDOI

VLSI module placement based on rectangle-packing by the sequence-pair

TL;DR: This paper attacks the biggest MCNC benchmark ami49 with a conventional wiring area estimation method, and obtain a highly promising placement, and proposes a solution space where each packing is represented by a pair of module name sequences, called a sequence-pair.
Proceedings ArticleDOI

B*-Trees: a new representation for non-slicing floorplans

TL;DR: An efficient, flexible, and effective data structure, B-trees for non-slicing floorplans, based on ordered binary trees and the admissible placement presented in [1], and a B-tree based simulated annealing scheme for floorplan design.
Proceedings ArticleDOI

A thermal-driven floorplanning algorithm for 3D ICs

TL;DR: A thermal-driven 3D floorplanning algorithm with CBA representation that can reduce the wirelength by 29% and reduce the maximum on-chip temperature by 56% is proposed.
Related Papers (5)