Patent
D flip-flop structure with flush path for high-speed boundary scan applications
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TLDR
In this article, a boundary scan cell includes a shift latch, an update latch, and a flushable latch that each have at least a respective data input and at least data output.Abstract:
A boundary scan cell includes a shift latch, an update latch and a flushable latch that each have at least a respective data input and at least a respective data output. The data output of the shift latch is coupled to the data input of the update latch. The boundary scan cell further includes control circuitry that controls operation of the flushable latch circuit. The control circuitry selects, as input data for the flushable latch, one of a functional logic signal and a boundary scan signal in response to a mode signal. If the mode signal indicates a test mode, the control circuitry selects the boundary scan signal as the input data and causes the flushable latch to flush through the input data to the data output of the flushable latch independent of a system clock signal. The boundary scan cell can be implemented as either an input or output cell and preferably is compliant with IEEE Std 1149.1.read more
Citations
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References
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Patent
Integrated test circuit
TL;DR: In this article, a test cell (12) provides boundary scan testing in an integrated circuit (10) consisting of two memories, a flip-flop (24) and a latch (26), for storing test data.
Patent
Testable programmable gate array and associated LSSD/deterministic test methodology
Beebe Wayne Kevin,Botala Sally,Scott Whitney Gould,Frank Ray Keyser,Larsen Wendell Ray,Palmer Ronald Raymond,Brian A. Worth +6 more
TL;DR: In this paper, a programmable gate array includes test subsystems for testing various functional subsystems of the PAG array, taking into account the interdependencies of the various subsystems and accordingly enabling fault isolation therein.
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Delay fault testing method and apparatus
TL;DR: In this article, a test cell (12) provides boundary scan testing in an integrated circuit (10) consisting of two memories, a flip-flop (24) and a latch (26), for storing test data.
Patent
VLSI test circuit apparatus and method
TL;DR: An LSSD MUX D flip flop includes a multiplexer, a master latch L1 and a slave latch L2 as discussed by the authors, which supports edge sensitive, level sensitive, functional, scan, freeze, flush, and test operations.
Patent
Boundary-scan bypass circuit for integrated circuit electronic component and circuit boards incorporating such circuits and components
TL;DR: In this paper, a method and apparatus for bypassing a boundary scan cell during functional operation of an electronic component provides a component output signal (such as a data signal) to a boundary-scan bypass circuit during normal functional operation.