Proceedings ArticleDOI
Delay fault testability modeling with temporal logic
G. Westerman,J.R. Heath,Charles E. Stroud +2 more
- pp 376-382
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TLDR
The application of temporal logic and STeP to delay fault testability modeling and analysis is presented.Abstract:
To ensure the quality of manufactured integrated circuits, it is important that designs be delay fault testable. A formal verification technique such as temporal logic can help avoid the large cost of dynamic simulation. Temporal logic is a formalism for evaluating the temporal behavior of systems. STeP, Stanford Temporal Prover, is a system developed at Stanford University to support computer-aided formal verification of concurrent and reactive systems based on temporal logic specification. The application of temporal logic and STeP to delay fault testability modeling and analysis is presented.read more
Citations
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Delay fault analysis using discrete event system approach
TL;DR: A formal verification method based on DES modeling techniques is developed for delay fault testability analysis, and logic delay gate models and circuit path delay models are constructed.
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References
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Book
The Temporal Logic of Reactive and Concurrent Systems: Specification
Amir Pnueli,Zohar Manna +1 more
Book ChapterDOI
Logics and Models of Real Time: A Survey
Rajeev Alur,Thomas A. Henzinger +1 more
TL;DR: This work surveys logic-based and automata-based languages and techniques for the specification and verification of real-time systems and discusses three syntactic extensions of temporal logic: time-bounded operators, freeze quantification, and time variables.
Journal ArticleDOI
On Delay Fault Testing in Logic Circuits
Chin Jen Lin,Sudhakar M. Reddy +1 more
TL;DR: Algorithms, based on a five-valued logic system, to accurately calculate the detection probability of path delay faults by random delay tests as well as to derive deterministic tests to detect pathdelay faults are proposed.
Book ChapterDOI
A hardware semantics based on temporal intervals
TL;DR: An interval-based temporal logic that permits the rigorous specification of a variety of hardware components and facilitates describing properties such as correctness of implementation is presented.