Patent
Double patterning methodology
Ken-Hsien Hsieh,Huang-Yu Chen,Jhih-Jian Wang,Cheng Kun Tsai,Tsong-Hua Ou,W. C. Huang,Ru-Gun Liu +6 more
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TLDR
In this article, the authors proposed a method of fabricating a semiconductor device by providing an integrated circuit layout plan, which contains a plurality of semiconductor features, and selecting a subset of the features for decomposition as part of a double patterning process.Abstract:
Provided is a method of fabricating a semiconductor device. The method includes providing an integrated circuit layout plan, the integrated circuit layout plan containing a plurality of semiconductor features. The method includes selecting a subset of the features for decomposition as part of a double patterning process. The method includes designating a relationship between at least a first feature and a second feature of the subset of the features. The relationship dictates whether the first and second features are assigned to a same photomask or separate photomasks. The designating is carried out using a pseudo feature that is part of the layout plan but does not appear on a photomask. The method may further include a double patterning conflict check process, which may include an odd-loop check process.read more
Citations
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Patent
Method of Manufacturing Semiconductor Device
TL;DR: In this article, a mask is formed selectively on a crystalline silicon film containing a catalyst element, and an amorphous silicon film is formed so as to cover the mask.
Proceedings ArticleDOI
Multiple patterning layout decomposition considering complex coloring rules
Hua-Yu Chang,Iris Hui-Ru Jiang +1 more
TL;DR: This paper model the MPLD problem as an exact cover problem, and proposes a fast and exact MPLD framework based on augmented dancing links, which can consider the basic and complex coloring rules simultaneously, and it can handle quadruple patterning and beyond.
Patent
Multi-patterning mask decomposition method and system
TL;DR: In this paper, a portion of a layout of a single layer of an integrated circuit is to be multi-patterned, and the patterns are divided into first and second groups, to be patterned on the single layer by a first mask or a second mask.
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Hybrid evolutionary algorithm for triple-patterning
Erdem Cilingir,Srini Arikati +1 more
TL;DR: In this paper, a computer-implemented method for validating a design includes generating, using the computer, a first graph representative of the design, when the computer is invoked to validate the design and decomposing, using a hybrid evolutionary algorithm to form a colored graph.
Patent
Method and apparatus for identifying double patterning color-seeding violations
TL;DR: In this paper, a method for automatically performing a double patterning (DP) color-seeding check in order to discover color seeding violations in an IC design layout is presented.
References
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Patent
System And Method For Providing Defect Printability Analysis Of Photolithographic Masks With Job-Based Automation
Linyong Pang,Fang-Cheng Chang +1 more
TL;DR: In this paper, a defect analysis tool with job-based automation can accurately and efficiently determine defect printability, which can be presented using different levels of detail to facilitate user review, and can be run in parallel.
Patent
Multi-patterning method
TL;DR: In this article, the layout of a DPT-layer of an integrated circuit generated by a place and route tool is represented by a plurality of polygons to be formed in the DPTlayer by a multi-patterning process.
Patent
Method for concurrent migration and decomposition of integrated circuit layout
Yao-Wen Chang,Chin-Hsiung Hsu +1 more
TL;DR: In this article, a method for concurrent migration and decomposition of an integrated circuit layout applicable to double patterning lithography techniques is provided, which includes cutting a sub-pattern of an initial pattern to configure a potentially conflicting pattern having separate or cutting sections.