Proceedings ArticleDOI
Dynamic thermal management for high-performance microprocessors
David Brooks,Margaret Martonosi +1 more
- pp 171-182
TLDR
This work investigates dynamic thermal management as a technique to control CPU power dissipation and explores the tradeoffs between several mechanisms for responding to periods of thermal trauma and the effects of hardware and software implementations.Abstract:
With the increasing clock rate and transistor count of today's microprocessors, power dissipation is becoming a critical component of system design complexity. Thermal and power-delivery issues are becoming especially critical for high-performance computing systems. In this work, we investigate dynamic thermal management as a technique to control CPU power dissipation. With the increasing usage of clock gating techniques, the average power dissipation typically seen by common applications is becoming much less than the chip's rated maximum power dissipation. However system designers still must design thermal heat sinks to withstand the worse-case scenario. We define and investigate the major components of any dynamic thermal management scheme. Specifically we explore the tradeoffs between several mechanisms for responding to periods of thermal trauma and we consider the effects of hardware and software implementations. With approximate dynamic thermal management, the CPU can be designed for a much lower maximum power rating, with minimal performance impact for typical applications.read more
Citations
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Proceedings ArticleDOI
Managing energy and server resources in hosting centers
TL;DR: Experimental results from a prototype confirm that the system adapts to offered load and resource availability, and can reduce server energy usage by 29% or more for a typical Web workload.
Proceedings ArticleDOI
Temperature-aware microarchitecture
Kevin Skadron,Mircea R. Stan,Wei Huang,Sivakumar Velusamy,Karthik Sankaranarayanan,David Tarjan +5 more
TL;DR: HotSpot is described, an accurate yet fast model based on an equivalent circuit of thermal resistances and capacitances that correspond to microarchitecture blocks and essential aspects of the thermal package that shows that power metrics are poor predictors of temperature, and that sensor imprecision has a substantial impact on the performance of DTM.
Journal ArticleDOI
Temperature-aware microarchitecture: Modeling and implementation
Kevin Skadron,Mircea R. Stan,Karthik Sankaranarayanan,Wei Huang,Sivakumar Velusamy,David Tarjan +5 more
TL;DR: HotSpot is described, an accurate yet fast and practical model based on an equivalent circuit of thermal resistances and capacitances that correspond to microarchitecture blocks and essential aspects of the thermal package that shows that power metrics are poor predictors of temperature, that sensor imprecision has a substantial impact on the performance of DTM, and that the inclusion of lateral resistances for thermal diffusion is important for accuracy.
Proceedings ArticleDOI
VirtualPower: coordinated power management in virtualized enterprise systems
Ripal Nathuji,Karsten Schwan +1 more
TL;DR: Experimental evaluations on modern multicore platforms highlight resulting improvements in online power management capabilities, including minimization of power consumption with little or no performance penalties and the ability to throttle power consumption while still meeting application requirements.
Proceedings ArticleDOI
No "power" struggles: coordinated multi-level power management for the data center
TL;DR: This paper proposes and validate a power management solution that coordinates different individual approaches and performs a detailed quantitative sensitivity analysis to draw conclusions about the impact of different architectures, implementations, workloads, and system design choices.
References
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Journal ArticleDOI
A 160 MHz 32 b 0.5 W CMOS RISC microprocessor
J. Montanaro,R. Witek,K. Anne,A.J. Black,Elizabeth M. Cooper,Daniel W. Dobberpuhl,P. Donahue,J. Eno,A. Farell,G. Hoeppner,D. Kruckemyer,Thomas H. Lee,P. Lin,L. Madden,Daniel C. Murray,M. Pearce,S. Santhanam,K. Snyder,R. Stephany,S.C. Thierauf +19 more
TL;DR: This custom VLSI implementation of a microprocessor architecture delivers 184 Drystone/MIPS at 162 MHz dissipating 0.5 W using an 1.5 V internal supply and Clock generation uses an on-chip PLL with 3.68 MHz input clock to minimize high frequency clock signals on the board.